Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

Abstract: The present invention presents a calibrator for a mobile station of a TDMA wireless communications system such that the calibrator calibrates a low-frequency clock to a high frequency clock locked to system timing. When the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and all clocks derived from it are turned off. Only the calibrated low-frequency clock remains operating to clock the sleep logic.

Abstract: The present invention presents a mobile station of a wireless communications system such that when the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and thus all high-frequency clocks derived from it are turned off. Only a low-frequency clock remains operating at all times to clock the sleep logic.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function, circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/0 interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

Abstract: A pixel modification unit is provided for carrying out a variety of raster graphic manipulations in a RISC graphics processor. The pixel modification unit comprises a logic function unit, a masking unit, and a byte mirror unit. The logic function unit can perform any of 16 different logic operations between each bit of a source operand and a destination operand. The source operand may be a bit map fixed data, while the destination operand is pixel data in the bit map corresponding to the graphics image to be modified. The masking unit can mask any or all bits of a destination operand so that the logic function unit does not operate on the masked bits. When masking is implemented, the output of the pixel modification unit is derived from the masked bits from the destination operand and the unmasked bits which were operated on by the logic function unit. The byte mirror unit horizontally reflects a figure in the bit map via reversing the bit order of data bytes retrieved from the bit map.

Abstract: A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.