Patents by Inventor Linlin Liu
Linlin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240369612Abstract: The present invention provides a measurement system and modeling method for radio frequency MOS device modeling. Electrodes that are correspondingly provided in a slave test structure and a master test structure of the measurement system are different, where a source and a drain of a second MOS device are respectively connected to corresponding test ports, and a gate is independently connected out to facilitate setting a corresponding bias voltage. The modeling method configures an initial value of each parasitic element in a subcircuit model by means of a test result of the measurement system, corrects the initial values of at least some parasitic elements, and finally obtains parasitic parameter values of the parasitic elements.Type: ApplicationFiled: December 30, 2021Publication date: November 7, 2024Applicant: SHANGHAI IC R & D CENTER CO., LTD.Inventors: Linlin LIU, Yueyi FENG, Quan WANG
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Publication number: 20240030337Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: ApplicationFiled: June 20, 2023Publication date: January 25, 2024Applicant: POWER INTEGRATIONS, INC.Inventors: ALEXEY KUDYMOV, LINLIN LIU, XIAOHUI WANG, JAMAL RAMDANI
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Patent number: 11776815Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: GrantFiled: May 25, 2022Date of Patent: October 3, 2023Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 11721753Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: GrantFiled: June 29, 2021Date of Patent: August 8, 2023Assignee: POWER INTEGRATIONS, INC.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Publication number: 20230221324Abstract: Disclosed herein are methods of detecting the presence or absence of exosomes, the method comprising detecting an exosomal biomarker in a sample obtained from a subject. Also disclosed herein is a system and a biosensor, each for detecting an exosomal biomarker as disclosed herein.Type: ApplicationFiled: January 11, 2022Publication date: July 13, 2023Inventors: Linlin LIU, Abhimanyu THAKUR, Wing Kar LI, Youngjin LEE, Chi-Man Lawrence WU
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Publication number: 20220406607Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: ApplicationFiled: May 25, 2022Publication date: December 22, 2022Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 11373873Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: GrantFiled: April 23, 2020Date of Patent: June 28, 2022Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Publication number: 20220013660Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: ApplicationFiled: June 29, 2021Publication date: January 13, 2022Applicant: Power Integrations, Inc.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Patent number: 11075294Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: GrantFiled: March 19, 2020Date of Patent: July 27, 2021Assignee: POWER INTEGRATIONS, INC.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Publication number: 20200287037Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: ApplicationFiled: March 19, 2020Publication date: September 10, 2020Applicant: Power Integrations, Inc.Inventors: Alexey KUDYMOV, Linlin LIU, Xiaohui WANG, Jamal RAMDANI
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Publication number: 20200258749Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: ApplicationFiled: April 23, 2020Publication date: August 13, 2020Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 10665463Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: GrantFiled: December 14, 2018Date of Patent: May 26, 2020Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 10629719Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.Type: GrantFiled: September 27, 2018Date of Patent: April 21, 2020Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, Linlin Liu, Xiaohui Wang, Jamal Ramdani
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Patent number: 10520543Abstract: The present invention discloses a test structure and a method for judging the de-embedding accuracy of RF devices, which comprises testing the S parameters of a target device test structure, an introduced device test structure and an auxiliary test structure, respectively. Then calculating de-embedding S parameters of the target device test structure and the introduced device test structure according to the above-tested results, respectively. Finally, calculating performance parameters of the target device test structure according to the above-calculated de-embedding S parameters. So, the accuracy of the de-embedding method is determined by comparing the consistency of the performance parameters. The present invention can directly judge the de-embedding accuracy and the applicable frequency range of a given de-embedding method by analyzing the testing data. Further, the using of the parallel test structure and the cascade test structure together can increase the reliability of the judgment results.Type: GrantFiled: October 28, 2014Date of Patent: December 31, 2019Assignees: SHANGHAI IC R&D CENTER CO., LTD, CHENGDU IMAGE DESIGN TECHNOLOGY CO., LTD.Inventor: Linlin Liu
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Publication number: 20190379007Abstract: The present disclosure discloses a manufacturing method for a high-resolution array organic film, and use thereof The high-resolution array organic film manufacturing method performs, by means of electrochemical deposition, polymerization of electrically active monomers on a high-resolution display screen array substrate to deposit and form a high-resolution array organic film. Also disclosed is a use of the manufactured high-resolution array organic film in manufacturing of OLED display screens. By employing electrochemical deposition to deposit the high-resolution array film on the high-resolution array substrate, the present disclosure provides a high-resolution film forming technique having simple operation, a low cost, film controllability, and precision up to 10 ?M.Type: ApplicationFiled: November 14, 2017Publication date: December 12, 2019Applicant: South China University of TechnologyInventors: Yuguang Ma, Linlin Liu, Rong Wang
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Publication number: 20190296011Abstract: A device structure for reducing FinFET parasitic resistance and a manufacturing method thereof.Type: ApplicationFiled: June 6, 2017Publication date: September 26, 2019Inventors: Ao GUO, Linlin LIU
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Publication number: 20190179991Abstract: A method and system for testing optimization and molding optimization of semiconductor devices. The testing optimization method is executed based on a test structure for testing the specific non-direct-current parameters, constructing an auxiliary structure of the test structure and testing the non-direct-current parameter, calculating the parallel parasitic resistance and the series parasitic resistance of the test structure based on the parasitic network model and the testing result of the auxiliary structure; performing linear fitting on the parallel parasitic resistance and the series parasitic resistance; and performing a direct-current testing on the test structure to obtain direct-current testing data and correcting the direct-current testing data based on the direct-current equivalent sub-circuit model.Type: ApplicationFiled: June 6, 2017Publication date: June 13, 2019Applicants: SHANGHAI IC R&D CENTER CO., LTD., CHENGDU IMAGE DESIGN TECHNOLOGY CO. LTD.Inventors: Linlin Liu, Ao Guo, Quan Wang, Wei Zhou
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Publication number: 20190139776Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.Type: ApplicationFiled: December 14, 2018Publication date: May 9, 2019Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: 10204791Abstract: A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.Type: GrantFiled: September 22, 2017Date of Patent: February 12, 2019Assignee: Power Integrations, Inc.Inventors: Alexey Kudymov, LinLin Liu, Jamal Ramdani
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Patent number: D1039667Type: GrantFiled: July 11, 2022Date of Patent: August 20, 2024Assignee: ZHEJIANG PREAIR ELECTRICAL APPLIANCE INDUSTRY CO., LTDInventors: Hailin Ye, Linlin Liu, Qiang Deng, Jiankai Shao