Abstract: A display device is disclosed. The display device includes a display array layer and a liquid crystal control layer superimposed on a display side of the display array layer. The liquid crystal control layer includes a first electrode layer, a liquid crystal layer and a second electrode layer; the display array layer includes first pixels and second pixels alternately arranged in a first direction; and the first electrode layer and the second electrode layer are configured to receive driving voltages, so as to allow liquid crystal molecules in the liquid crystal layer to rotate to form first light deflection regions and second light deflection regions that are alternately arranged in the first direction, so as to form a first view point and a second view point.

Abstract: Disclosed are a method and a system for comprehensive evaluation of organic compound and heavy metal pollution in water based on fish electro-cardio, and fish electro-cardio signals are acquired by a real-time and miniaturized fish electro-cardio acquisition system which includes a real-time and miniaturized fish electro-cardio acquisition device, then a change of the electro-cardio index in a QT interval is obtained for assessing the corresponding organic compound in water to be tested, and a change of the electro-cardio index in a QRS interval is obtained for assessing the corresponding heavy metal in water to be tested. Based on fish electro-cardio acquired continuously on-line in real-time while keeping fish swims in a normal state and the water quality parameters acquired by various water quality sensors, water quality is online analyzed and water sudden pollution is online monitored and assessed.

Abstract: An optical detection sensor is disclosed. The optical detection sensor includes a converter configured to receive non-visible light, convert the non-visible light into visible light, and emit the visible light; and a visible light solid-state image sensor. The converter is located on a light incident side of the visible light solid-state image sensor, and the visible light solid-state image sensor is configured to receive the visible light to generate an electron flow, convert information of the electron flow into data information, and output the data information.

Abstract: The present invention discloses a test structure and a method for judging the de-embedding accuracy of RF devices, which comprises testing the S parameters of a target device test structure, an introduced device test structure and an auxiliary test structure, respectively. Then calculating de-embedding S parameters of the target device test structure and the introduced device test structure according to the above-tested results, respectively. Finally, calculating performance parameters of the target device test structure according to the above-calculated de-embedding S parameters. So, the accuracy of the de-embedding method is determined by comparing the consistency of the performance parameters. The present invention can directly judge the de-embedding accuracy and the applicable frequency range of a given de-embedding method by analyzing the testing data. Further, the using of the parallel test structure and the cascade test structure together can increase the reliability of the judgment results.

Abstract: Embodiments described herein generally relate to a method and apparatus for fabricating a chamber component for a plasma process chamber. In one embodiment a chamber component used within a plasma processing chamber is provided that includes a metallic base material comprising a roughened non-planar first surface, wherein the roughened non-planar surface has an Ra surface roughness of between 4 micro-inches and 80 micro-inches, a planar silica coating formed over the roughened non-planar surface, wherein the planar silica coating has a surface that has an Ra surface roughness that is less than the Ra surface roughness of the roughened non-planar surface, a thickness between about 0.2 microns and about 10 microns, less than 1% porosity by volume, and contains less than 2E12 atoms/centimeters2 of aluminum.

Abstract: The present disclosure discloses a manufacturing method for a high-resolution array organic film, and use thereof The high-resolution array organic film manufacturing method performs, by means of electrochemical deposition, polymerization of electrically active monomers on a high-resolution display screen array substrate to deposit and form a high-resolution array organic film. Also disclosed is a use of the manufactured high-resolution array organic film in manufacturing of OLED display screens. By employing electrochemical deposition to deposit the high-resolution array film on the high-resolution array substrate, the present disclosure provides a high-resolution film forming technique having simple operation, a low cost, film controllability, and precision up to 10 ?M.

Abstract: A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.

Abstract: A data source simulation platform includes: a transmitting side and a receiving side. The transmitting side includes a parameter initializing module, a parameter calculation module, and a subframe data module. The receiving side includes a system function configuration module, a downlink initial synchronization module, an error control module, a time-frequency estimation module, and a data parsing module. The parameter initializing module is configured to construct simulation parameters, configure a subframe structure, and simulate a raw data block to be transmitted from a protocol data unit packet of a media access control layer to a physical layer. The parameter calculation module is configured to calculate set simulation parameters. The subframe data module is configured to provide independent data for an air-interface monitoring device, the data being in a modular design and independently corresponding to each submodule.

Abstract: A display substrate, a method for manufacturing the same and a display device are provided. The method includes steps of forming a common electrode line, a semiconductor pattern, and a data line on a base substrate, so that the semiconductor pattern is located between the common electrode line and the data line; and irradiating the semiconductor pattern by using light in a predetermined wavelength range from a side of the base substrate distal to the semiconductor pattern, to generate a dangling-bond defect state in a band gap of the semiconductor pattern.

Abstract: A device structure for reducing FinFET parasitic resistance and a manufacturing method thereof.

Abstract: A photographic mask is provided in the present disclosure. The photographic mask includes a silicon-on-insulator (SOI) base and a stepped opening formed in the SOI base. The SOI base includes a silicon substrate, a median layer and a silicon layer, the median layer is arranged between the insulator substrate and the insulator layer. The stepped opening includes a first opening portion and a second opening portion, the first opening portion penetrates through the silicon layer and has a first opening area; the second opening portion at least penetrates through the silicon substrate and is aligned with the first opening portion. The second opening portion has a second opening area greater than the first opening area of the first opening portion. The present disclosure further provides a method for making a photographic mask.

Abstract: The present invention relates to a polishing liquid for CMP and preparation method thereof. 100 parts by weight of the polishing liquid comprises: 0.1 to 50 parts of abrasive, 0.001 to 0.4 part of surfactant, 0.001 to 0.6 part of film former, and 0.05 to 10 parts of pH regulator, and 0.01 to 4 parts of polishing accelerator, and deionized water in balance; and the pH value of the polishing liquid is 9.5 to 12.5. When a GaAs wafer is polished with the polishing liquid of the present invention, various performance indexes such as polishing removal rate, surface roughness and TTV of the polished wafer are excellent, and the polishing liquid is easy to be washed away, does not corrode equipment, and does not introduce harmful metal ions. The polishing liquid of the present invention can be used continuously and circularly for a long period of 6 to 10 hours, which greatly saves resources and reduces the use cost of the polishing liquid.

Abstract: A method and system for testing optimization and molding optimization of semiconductor devices. The testing optimization method is executed based on a test structure for testing the specific non-direct-current parameters, constructing an auxiliary structure of the test structure and testing the non-direct-current parameter, calculating the parallel parasitic resistance and the series parasitic resistance of the test structure based on the parasitic network model and the testing result of the auxiliary structure; performing linear fitting on the parallel parasitic resistance and the series parasitic resistance; and performing a direct-current testing on the test structure to obtain direct-current testing data and correcting the direct-current testing data based on the direct-current equivalent sub-circuit model.

Abstract: The present application discloses a dredging system for a pre-paved gravel foundation bed surface in open sea deep water, including a dredging mechanism, which includes a dredging suction head, a power component and a dredging pipeline, wherein the dredging suction head is connected with the dredging pipeline; the dredging pipeline is communicated with the power component; the dredging suction head includes at least one ridge surface suction port and at least one furrow suction port; the openings of all the furrow suction ports are lower than those of all the ridge surface suction ports; a lifting mechanism, which is connected with the dredging suction head and is used for lifting the dredging suction head to the gravel foundation bed surface; a moving mechanism, which is connected with the lifting mechanism and is used for driving the dredging suction head to move within a dredging range of the gravel foundation bed surface.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

Abstract: A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.

Abstract: A high-voltage field effect transistor a heterojunction is disposed between the first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. The first insulation layer is disposed between the first passivation layer and the second passivation layer, and the second passivation layer is disposed between the first insulation layer and the second insulation layer. A gate dielectric disposed between the second semiconductor material and the first passivation layer. A gate electrode is disposed above the gate dielectric. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material.