Abstract: A semiconductor device includes: a substrate; an epitaxial structure located on a side of the substrate; an electrode structure located on a side of the epitaxial structure away from the substrate; and at least one odd-mode resistor located outside the first active region and electrically connected to the electrode structure. Each odd-mode resistor of the at least one odd-mode resistor includes a first resistor electrode and a second resistor electrode. In a same odd-mode resistor, the first resistor electrode and the second resistor electrode both form ohmic contact with the two-dimensional electron gas in the second active region, and along an arrangement direction of the first resistor electrode and the second resistor electrode, a two-dimensional-electron-gas conductive channel exists between the first resistor electrode and the second resistor electrode.

Abstract: This application relates to the field of model aircraft technology, and in particular to a miniature retractable undercarriage.

Abstract: Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, the semiconductor device including a substrate, an epitaxial structure located at a side of the substrate, a plurality of gates located at a side of the epitaxial structure away from the substrate, the gates extending along a first direction, and the plurality of the gates being arranged along a second direction, the first direction and the second direction intersecting with each other and each being parallel to a plane where the substrate is located, the plurality of the gates include a first gate and a second gate, and along the second direction, the first gate being located at a side of the second gate near an edge of the semiconductor device, and the highest temperature of the first gate is T1, and the highest temperature of the second gate is T2, wherein (T2?T1)/T1?20%.

Abstract: Embodiments of the present disclosure disclose a semiconductor device including a plurality of sources, a plurality of gates, and a plurality of drains located in an active area. In the active area, the sources, the gates, and the drains are alternately arranged along a first direction, and along the first direction, the sources include two sources respectively closest to ends of the arrangement, and any one of the gates is located between one of the sources and one of the drains, a length of at least a source located at the center along the first direction is greater than lengths of sources located at both ends along the first direction. The semiconductor device further includes a plurality of rows of through holes extending through a substrate and a multilayer semiconductor layer, a plurality of rows of the through holes are arranged along the first direction, and an orthographic projection.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: A semiconductor device and its fabrication method are provided. The method includes forming a core layer on a first region of a base substrate layer; forming sidewall spacer layers on sidewalls of two sides of the core layer along a first direction; forming a filling layer on a second region between adjacent sidewall spacer layers which are arranged along the first direction; forming a first dividing trench in the filling layer on the second region to divide the filling layer along a second direction, where sidewalls of the first dividing trench, arranged along the first direction, expose corresponding sidewall spacer layers; forming a second dividing trench in the core layer to divide the core layer along the second direction; forming a second dividing layer in the second dividing trench when forming a first dividing layer in the first dividing trench; and removing the filling layer and the core layer.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: A semiconductor device and its fabrication method are provided. The method includes forming a core layer on a first region of a base substrate layer; forming sidewall spacer layers on sidewalls of two sides of the core layer along a first direction; forming a filling layer on a second region between adjacent sidewall spacer layers which are arranged along the first direction; forming a first dividing trench in the filling layer on the second region to divide the filling layer along a second direction, where sidewalls of the first dividing trench, arranged along the first direction, expose corresponding sidewall spacer layers; forming a second dividing trench in the core layer to divide the core layer along the second direction; forming a second dividing layer in the second dividing trench when forming a first dividing layer in the first dividing trench; and removing the filling layer and the core layer.

Abstract: Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Abstract: Nanoparticulate carrier formulations are useful to solubilize, deliver, and target hydrophobic drugs for treating diseases including cancer and bacterial infections. The formulations contain amphiphilic peptides having a hydrophobic portion and a positively charged hydrophilic portion. The peptides self-associate at nonacidic pH to form mi-celles with a spherical nanoparticle morphology. The hydrophobic core of the nano-particles encapsulates hydrophobic drugs, including antitumor agents, increasing their solubility in water and allowing them to be targeted, for example, to cancer cells. The positively charged surface of the nanoparticles, together with an optional targeting moiety such as an RGD peptide, allows the nanoparticles to bind selectively to mammalian cells and bacterial cells, including cancer cells that overexpress integrin receptors.

Abstract: The present invention relates to crystalline forms of pyrroloquinoline quinone disodium salt. The present invention provides crystalline Form A and crystalline Form B of pyrroloquinoline quinone disodium salt, and the methods and uses for the preparation thereof. The X-ray powder diffraction patterns of crystalline Form A and crystalline Form B are as shown by FIG. 1 and FIG. 5, respectively. The crystalline forms of the present invention have low moisture absorption and high stability, as well as excellent use and storage performances.