Abstract: The invention is a software structure for software components that adds greater flexibility to them. This structure is composed of the following parts: On Memory, Structure, On File Structure and On Memory On File Interface. These three parts are united into the same execution environment like a whole, performing functions like the older components but more complex than the older ones.

Abstract: The present invention discloses a novel method to implement a Smart Device Network Application Infrastructure (SDNA) that supports and facilitates the development, deployment and management of device networks and device network applications. The Smart Device Network Application infrastructure (SDNA) refers to an integrated processing platform that supports and facilitates the development, deployment and management of distributed applications based on device networks. It involves the concurrent execution of several processes that interact to provide support and resources for said applications.

Abstract: The present invention comprises a method of source routing to implement device-to-device communications across a hybrid distributed device control network. The method is based in packet communications in which packets are structured so that they can be readily converted between communications protocols, and in which packets enclose routing information and parameters.

Abstract: The present invention is a software architecture that provides high versatility and performance. This architecture is composed of two dimensions: the first one belongs in the application level, and the second in the multicore dimension. The application dimension is related to the different applications based in the conceptual model of abstractions exposed in this patent. The multicore dimension is related to the applications dimension instantiated several times in the same computer (multiple processors) or in several computers. All the cores within the multicore dimension are related in order to share information and integrate all the architecture''s applications. The multicore architecture avoids bottlenecks in the simultaneous execution of multiple applications on the same computer by means of a large virtual core composed of small interconnected cores.

Abstract: Low processing power microprocessors are cheap and represent a great solution for automation, control, basic signal processing and other problems. A microprocessor's intelligence derives from the program it executes. The Smart Internetworking Operating System (SIOS) is a multitasking operating system capable of operating in low processing power platforms, such as 8-bit microprocessors, SIOS supports rapid development of complete applications since task programming is based on SIOS instructions, instead of on the underlying microprocessor's native language. The SIOS instruction set allows the execution of both simple and complex operations, which speed up application development since programmers need not be concerned with the microprocessor-specific details, and can concentrate on developing intelligent operation routines according to the requirements of the problem at hand.

Abstract: The present invention comprises a method of source routing to implement device-to-device communications across a hybrid distributed device control network. The method is based in packet communications in which packets are structured so that they can be readily converted between communications protocols, and in which packets enclose routing information and parameters.

Abstract: The invention is a software structure for software components that adds greater flexibility to them. This structure is composed of the following parts: On Memory, Structure, On File Structure and On Memory On File Interface.

Abstract: The invention is a software structure for software components that adds greater flexibility to them. This structure is composed of the following parts: On Memory, Structure, On File Structure and On Memory On File Interface. This three parts are united into the same execution environment like a whole, performing functions like the older components but more complex than the older ones. The inner structure of an ESC is a three tier model that contains a piece of it always loaded in memory (On Memory Structure), the other (On File Structure) is loaded into pieces by a File Component Loader, and it works loading the pertinent data of the file extension. The On memory Structure and the On File Structure are communicated by an inner interface object (On Memory-On File interface) that provides a interface between the essential parts of an Enhanced Software Component establishing a two ways communication channel. This Interface is a common one for all ESC and it can be enriched in order to support specialized cases.

Abstract: The present invention comprises a method of source routing to implement device-to-device communications across a hybrid distributed device control network. The method is based in packet communications in which packets are structured so that they can be readily converted between communications protocols, and in which packets enclose routing information and parameters.

Abstract: Low processing power microprocessors are cheap and represent a great solution for automation, control, basic signal processing and other problems. A microprocessor's intelligence derives from the program it executes. The Smart Internetworking Operating System (SIOS) is a multitasking operating system capable of operating in low processing power platforms, such as 8-bit microprocessors. SIOS supports rapid development of complete applications since task programming is based on SIOS instructions, instead of on the underlying microprocessor's native language. The SIOS instruction set allows the execution of both simple and complex operations, which speeds up application development since programmers need not be concerned with the microprocessor-specific details, and can concentrate on developing intelligent operation routines according to the requirements of the problem at hand.

Abstract: The present invention is a software architecture that provides high versatility and performance. This architecture is composed of two dimensions: the first one belongs in the application level, and the second in the multicore dimension. The application dimension is related to the different applications based in the conceptual model of abstractions exposed in this patent. The multicore dimension is related to the applications dimension instantiated several times in the same computer (multiple processors) or in several computers. All the cores within the multicore dimension are related in order to share information and integrate all the architecture's applications. The multicore architecture avoids bottlenecks in the simultaneous execution of multiple applications on the same computer by means of a large virtual core composed of small interconnected cores.