Abstract: The present disclosure provides a testkey structure and a monitoring method with a testkey structure, and the testkey structure includes a first diffusion region and a second diffusion region, a first gate and a second gate, a first epitaxial layer and a second epitaxial layer, and an input pad and an output pad. The first diffusion region and the second diffusion region are disposed in a substrate. The first gate and the second gate are disposed on a substrate, across the first diffusion region and the second diffusion region respectively. The first epitaxial layer and the second epitaxial layer are respectively disposed on the second diffusion region and the first diffusion region, separately disposed between the first gate and the second gate. The input pad and the output pad are electrically connected to the first epitaxial layer and the second epitaxial layer respectively.

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Abstract: The invention provides a semiconductor testkey, which comprises a testkey on a substrate, the testkey comprises a first resistor pattern, a second resistor pattern and a third resistor pattern arranged in a strip, the distance between the first resistor pattern and the second resistor pattern is defined as a first distance, and the distance between the second resistor pattern and the third resistor pattern is defined as a second distance, the first resistor pattern, the second resistor pattern and the third resistor pattern have the same pattern, and the second distance is larger than the first distance.

Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Abstract: A radiofrequency device includes a semiconductor substrate, an inductor structure, a shielding structure, and a mask pattern. The semiconductor substrate includes a first region and a second region. The inductor structure is disposed on the first region of the semiconductor substrate. The shielding structure is disposed on the first region of the semiconductor substrate and located between the inductor structure and the semiconductor substrate in a vertical direction. The mask pattern is disposed on the semiconductor substrate. A first portion of the mask pattern is disposed on the shielding structure and directly contacts the shielding structure, and a top surface of the shielding structure is completely covered by the first portion of the mask pattern.

Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.

Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.