Abstract: A method of erasing a split gate flash memory cell is provided, which can be used in the operation of a split gate flash memory cell to increase the number of its rewritable cycles. The improvement is remarkable especially for flash memory cells while its floating gate channel length is under a 0.4 .mu.m-feature size.

Abstract: A method for forming oxides on buried N.sup.+ -type regions in a memory cell fabrication process, suitable for forming oxides on the bury N.sup.+ -type regions before self-aligned MOS device etching, comprises: (1) implanting a high concentration of impurity into the buried N.sup.+ -type regions; (2) annealing the chip; and (3) executing a dry oxide process and then a wet oxidation process to the chip, thereby preventing damage to the edges of buried N.sup.+ -type regions caused by non-uniform thickness of oxides on buried regions during self-aligned MOS etching and resolving the problem of non-uniform oxides on buried N.sup.+ -type regions.

Abstract: A method for manufacturing self-aligned split-gate flash memory cells wherein the split-gate structure is formed by a self-aligned approach, so that the length of a channel can be precisely controlled. Furthermore, sources and drains are formed separately by executing different implantations, so that the dopant parameters of the sources and drains can be changed, based on desired and possibly different characteristics.