Abstract: The present invention provides a display substrate and a method for driving the same, and a display apparatus. The display substrate comprises pixel groups repeatedly arranged, each of the pixel groups comprises two first sub-pixels, eight second sub-pixels and two third sub-pixels, and each of the pixel groups comprises four pixel columns, two first sub-pixels are sequentially arranged in a first pixel column of each of the pixel groups and two third sub-pixels are sequentially arranged in a third pixel column of each of the pixel groups, wherein, each of the first sub-pixels is disposed so as to correspond to two second sub-pixels in a pixel column adjacent thereto, and each of the third sub-pixels is disposed so as to correspond to two second sub-pixels in a pixel column adjacent thereto.

Abstract: A display substrate, a driving method thereof and a display device are disclosed. The display substrate includes repeatedly arranged pixel groups. Each pixel group includes a first sub-pixel group, a second sub-pixel group, a third sub-pixel group and a fourth sub-pixel group. Each of the first sub-pixel group, the second sub-pixel group, the third sub-pixel group and the fourth sub-pixel group includes four pixel columns. The display substrate, the driving method thereof and the display device reduce the number of sub-pixels in the whole display device and hence reduce the difficulty in the manufacturing process of the display device and the cost on the premise of ensuring that the display device obtains a high resolution.

Abstract: A pixel driving circuit, array substrate and display apparatus, comprise: data line for providing data voltage; gate line for providing scanning voltage; first power supply line for providing first power supply voltage; second power supply line for providing second power supply voltage; light emitting device connected to second power supply line; driving transistor connected to first power supply line; storage capacitor having first terminal connected to gate of driving transistor and configured to transfer information to gate of driving transistor; resetting unit configured to reset voltage across storage capacitor as predetermined signal voltage; data writing unit configured to write information into second terminal of storage capacitor; compensating unit configured to write information into first terminal of storage capacitor; and light emitting control unit configured to write first power supply voltage into second terminal of storage capacitor and control driving transistor to drive light emitting device

Abstract: A pixel driving circuit, driving method thereof, an array substrate and display apparatus, the pixel driving circuit comprises: a data line for providing a data voltage; a gate line for providing a scanning voltage; a first power supply line for providing a first power supply voltage; a second power supply line for providing a second power supply voltage; a light emitting device connected to the second power supply line; a driving transistor connected to the first power supply line; a storage capacitor having a first terminal connected to a gate of the driving transistor and configured to transfer information including the data voltage to the gate of the driving transistor; a resetting unit configured to reset a voltage across the storage capacitor as a predetermined signal voltage; a data writing unit configured to write information including the data voltage into the second terminal of the storage capacitor; a compensating unit configured to write information including a threshold voltage of the driving tra

Abstract: There provide a pixel driving circuit and driving method thereof, an array substrate and display apparatus, wherein the pixel driving circuit comprises: a data line; a gate line; a first power supply line; a second power supply line; a light emitting device connected to the second power supply line; a driving transistor connected to the first power supply line; a storage capacitor having a first terminal connected to a gate of the driving transistor and configured to transfer information including the data voltage to the gate of the driving transistor; a resetting unit configured to reset a voltage across the storage capacitor as a predetermined signal voltage; a data writing unit configured to write information including the data voltage into the second terminal of the storage capacitor; a compensating unit configured to write information including a threshold voltage of the driving transistor and information of the first power supply voltage into the first terminal of the storage capacitor; and a light emit

Abstract: This disclosure relates to a display panel, an organic light emitting diode display and a display device comprising the display panel. The display panel according to one aspect of this disclosure comprises a plurality of pixels each comprising a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein the first sub-pixel and the second sub-pixel are arranged in the row direction, the first sub-pixel in each pixel is adjacent to the first sub-pixel in a pixel adjacent in the row direction, the second sub-pixel in each pixel is adjacent to the second sub-pixel in another pixel adjacent in the row direction, the geometrical center of the third sub-pixel in each pixel is distributed uniformly on the display panel. By means of the display panel of this disclosure, the area of the light emitting area in the pixel can be increased, the aperture ratio can be improved, so as to realize high display quality.

Abstract: Subject matter described herein includes a multi-layer search-engine index. Accordingly, the search-engine index is divided into multiple indexes, each of which includes a respective set of information used to serve (i.e., respond to) a query. One index includes a term index, which organizes a set of terms that are found among a collection of documents. Another index includes a document index, which organizes a set of documents that are searchable. A computing device is used to serve the search-engine index (i.e., to analyze the index when identifying documents relevant to a search query). For example, a solid-state device might be used to serve the multi-layer search-engine index.

Abstract: In some examples, pointing functionality is integrated with one or more keys of a keyboard. For instance, a precision pointing surface can be integrated with a key, such as the “J” key, that allows a user to manipulate a pointer on a display. In some situations, one or more touch-sensitive surfaces can also be integrated on other keys to provide clicking functionality. For example, a touch-sensitive surface can be integrated onto a left portion of a spacebar to allow left clicking capability and a touch-sensitive surface can be integrated onto a right portion of the spacebar to allow right clicking capability. In some instances, one or more touch-sensitive surfaces can be used to enable and disable the precision pointing surfaces and other touch-sensitive surfaces.

Abstract: Subject matter described herein includes a multi-layer search-engine index. Accordingly, the search-engine index is divided into multiple indexes, each of which includes a respective set of information used to serve (i.e., respond to) a query. One index includes a term index, which organizes a set of terms that are found among a collection of documents. Another index includes a document index, which organizes a set of documents that are searchable. A computing device is used to serve the search-engine index (i.e., to analyze the index when identifying documents relevant to a search query). For example, a solid-state device might be used to serve the multi-layer search-engine index.

Abstract: Architecture employs an iterative process that incrementally discovers inter-component interactions and explores local state spaces within each component. Thus, the architecture lazily constructs the behavior of the environment of a component in the target software system, and integrates the construction of the inter-component interactions with the model checking process itself, and hence, does not need to eagerly construct the interface process. Component-based state space reduction is applied during the exploration of the whole system. The architecture decomposes a target software system into a set of loosely coupled components where interactions between the components tend to be significantly simpler than interactions within each component. An iterative algorithm facilitates the component-based state space reduction, which is exponential, on the real large-scale software systems.

Abstract: Architecture that performs incremental computing for web searches by employing methods at least for storing the results of repeat queries on unchanged webpages and for computing results for the repeated queries. The architecture includes one or more algorithms for pre-computing query results on index servers, for only selectively choosing index servers whose result for a query change for a query computation process, and for re-using the unchanged web pages stored in the cache and computing results upon changed index and unchanged index separately.

Abstract: Architecture that performs incremental computing for web searches by employing methods at least for storing the results of repeat queries on unchanged webpages and for computing results for the repeated queries. The architecture includes one or more algorithms for pre-computing query results on index servers, for only selectively choosing index servers whose result for a query change for a query computation process, and for re-using the unchanged web pages stored in the cache and computing results upon changed index and unchanged index separately.

Abstract: Architecture employs an iterative process that incrementally discovers inter-component interactions and explores local state spaces within each component. Thus, the architecture lazily constructs the behavior of the environment of a component in the target software system, and integrates the construction of the inter-component interactions with the model checking process itself, and hence, does not need to eagerly construct the interface process. Component-based state space reduction is applied during the exploration of the whole system. The architecture decomposes a target software system into a set of loosely coupled components where interactions between the components tend to be significantly simpler than interactions within each component. An iterative algorithm facilitates the component-based state space reduction, which is exponential, on the real large-scale software systems.

Abstract: Methods and architectures for automatic filter generation are described. In an embodiment, these filters are generated in order to block inputs which would otherwise disrupt the normal functioning of a program. An initial set of filter conditions is generated by analyzing the path of a program from a point at which a bad input is received to the point at which the malfunctioning of the program is detected and creating conditions on an input which ensure that this path is followed. Having generated the initial set of filter conditions, the set is made less specific by determining which instructions do not influence whether the point of detection of the attack is reached and removing the filter conditions which correspond to these instructions.

Abstract: Subject matter described herein includes a multi-layer search-engine index. Accordingly, the search-engine index is divided into multiple indexes, each of which includes a respective set of information used to serve (i.e., respond to) a query. One index includes a term index, which organizes a set of terms that are found among a collection of documents. Another index includes a document index, which organizes a set of documents that are searchable. A computing device is used to serve the search-engine index (i.e., to analyze the index when identifying documents relevant to a search query). For example, a solid-state device might be used to serve the multi-layer search-engine index.

Abstract: A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

Abstract: An array substrate includes a base substrate, a plurality of gate lines, a plurality of data lines and a pixel matrix. The plurality of gate lines and the plurality of data lines define pixel areas. The pixel matrix is formed on each pixel area, and includes a plurality of pixel columns and pixel rows. Each pixel column has a first pixel group and a second pixel group. The first pixel group is electrically connected to a first gate line adjacent to the pixel column. The second pixel group is electrically connected to a second gate line adjacent to the pixel column. Each pixel row is electrically connected to one data line adjacent to the pixel column.

Abstract: A distributed system checker may check a distributed system against events to detect bugs in the distributed system. The events may include machines crashes, network partitions, and packet losses, for example. The distributed system checker may check a distributed system that can have multiple threads and multiple processes running on multiple nodes. To obtain control over a distributed system, a distributed system checker may insert an interposition layer between a process and the operating system on each node.

Abstract: A distributed system checker may check a distributed system against events to detect bugs in the distributed system. The events may include machines crashes, network partitions, and packet losses, for example. The distributed system checker may check a distributed system that can have multiple threads and multiple processes running on multiple nodes. To obtain control over a distributed system, a distributed system checker may insert an interposition layer between a process and the operating system on each node.

Abstract: A method for bounded model checking of arbitrary Linear Time Logic temporal properties. The method comprises translating properties associated with temporal operators F(p), G(p), U(p, q) and X(p) into property checking schemas comprising Boolean satisfiability checks, wherein F represents an eventuality operator, G represents a globally operator, U represents an until operator and X represents a next-time operator. The overall property is checked in a customized manner by repeated invocations of the property checking schemas for F(p), G(p), U(p, q), X(p) operators and standard handling of atomic propositions and Boolean operators.