Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

Abstract: An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to keep such code inaccessible to users and user-controlled software programs. A memory architecture includes first and second protected memory spaces, respectively storing operating system instructions and a decrypted version of the encrypted information. The first protected memory space may further store a table linking the locations of the encrypted and/or hidden, decrypted information with a decryption and/or authorization key. The system includes the memory architecture and a processor for executing instructions, and the method loads, stores and operates on the encrypted and/or hidden information according to the memory architecture functionality and/or constraints.

Abstract: In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

Abstract: In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: A method for supporting input/output for a virtual machine. The method includes the step of executing virtual machine application instructions, wherein the application instructions are executed using micro architecture code of a processor architecture. An I/O access is received from the virtual machine application. Virtual memory protection is used to generate an exception, wherein the exception is caused by the I/O access. A single step mode is entered to perform the I/O access using a host operating system. State data for the virtual machine application is updated in accordance with the I/O access. Subsequently, execution of the virtual machine application is resumed.

Abstract: An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to keep such code inaccessible to users and user-controlled software programs. A memory architecture includes first and second protected memory spaces, respectively storing operating system instructions and a decrypted version of the encrypted information. The first protected memory space may further store a table linking the locations of the encrypted and/or hidden, decrypted information with a decryption and/or authorization key. The system includes the memory architecture and a processor for executing instructions, and the method loads, stores and operates on the encrypted and/or hidden information according to the memory architecture functionality and/or constraints.

Abstract: An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to keep such code inaccessible to users and user-controlled software programs. A memory architecture includes first and second protected memory spaces, respectively storing operating system instructions and a decrypted version of the encrypted information. The first protected memory space may further store a table linking the locations of the encrypted and/or hidden, decrypted information with a decryption and/or authorization key. The system includes the memory architecture and a processor for executing instructions, and the method loads, stores and operates on the encrypted and/or hidden information according to the memory architecture functionality and/or constraints.

Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.

Abstract: A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

Abstract: A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

Abstract: A method for determining a process to use for converting instructions in a target instruction set to instructions in a host instructions set including the steps of executing code morphing software including an interpreter and a translator to generate host instructions from target instructions, detecting at intervals whether the interpreter or the translator is executing, increasing a count if the interpreter is executing and decreasing the count if the translator is executing, and changing from interpreting to translating a sequence of target instructions when the count reaches a selected maximum.

Abstract: Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.

Abstract: In a computer system that translates target instructions from a target instruction set into host instructions from a host instruction set, a method for checking a sequence of target instructions for changes. The method includes testing whether the target instructions at a memory location have changed subsequent to the translating by examining a bit indicator associated with the memory location and determining whether the testing is slowing the operation of the computer system. If the testing is slowing the operation of the computer system, a checking process initiated, which includes storing a copy of the sequence of target instructions and comparing the copy with the sequence of target instructions.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.