Patents by Inventor Lionel Belnet

Lionel Belnet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7949866
    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: May 24, 2011
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7849310
    Abstract: A data processing system including a processor operable in a plurality of modes and in either a secure domain or a non-secure domain. The system includes at least one secure mode being a mode in the secure domain, at least one non-secure mode being a mode in the non-secure domain, and a monitor mode. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. Switching between the secure and non-secure modes takes place via the monitor mode and the processor is operable at least partially in the monitor mode to execute a monitor program managing switching between the secure and non-secure modes.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 7, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7840001
    Abstract: Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer ‘n’ of the groups of data elements over a corresponding ‘n’ processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the ‘n’ of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: November 23, 2010
    Assignee: ARM Limited
    Inventors: Lionel Belnet, Stephane Eric Sebastien Brochier, Simon Andrew Ford
  • Patent number: 7661104
    Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 9, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastian Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Patent number: 7661105
    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 9, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20090320048
    Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
    Type: Application
    Filed: November 17, 2003
    Publication date: December 24, 2009
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Publication number: 20090259846
    Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 15, 2009
    Applicant: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephanie Eric Sebastien Brochier
  • Patent number: 7487367
    Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 3, 2009
    Assignee: ARM Limited
    Inventors: Lionel Belnet, Nicolas Chaussade, Simon Charles Watt, Peter Guy Middleton
  • Patent number: 7448050
    Abstract: In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 4, 2008
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, Michael Robert Nonweiler, Dominic Hugo Symes
  • Patent number: 7383587
    Abstract: A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 3, 2008
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7325083
    Abstract: In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: January 29, 2008
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Patent number: 7305534
    Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 4, 2007
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton
  • Patent number: 7305712
    Abstract: There is a provided a data processing system comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and wherein said processor is responsive to a switching request to initiate a switch between a secure mode and a non-secure mode under control of a mode switching program starting at a location specified by an exception vector associated with said switching request.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 4, 2007
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20070104324
    Abstract: Data processing apparatus and methods are provided. One data processing apparatus comprises: a plurality of pipelined stages, each of the plurality pipelined stages being operable in each processing cycle to receive a group of data elements from an earlier pipelined stage; permute logic operable to buffer ‘n’ of the groups of data elements over a corresponding ‘n’ processing cycles thereby creating a bubble within pipelined stages, and forwarding logic operable, once the ‘n’ of the groups of data elements have been buffered by the permute logic, to forward permuted groups of data elements comprising the data elements reordered by the permute logic to fill the bubble within the pipelined stages.
    Type: Application
    Filed: November 4, 2005
    Publication date: May 10, 2007
    Applicant: ARM Limited
    Inventors: Lionel Belnet, Stephane Brochier, Simon Ford
  • Patent number: 7149862
    Abstract: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: December 12, 2006
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Peter James Aldworth, Simon Charles Watt, Lionel Belnet, David Hennah Mansell
  • Patent number: 7124274
    Abstract: An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: October 17, 2006
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Michael Robert Nonweiler
  • Patent number: 7117284
    Abstract: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: October 3, 2006
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Jonathan Sean Callan
  • Publication number: 20050160210
    Abstract: There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said excepti
    Type: Application
    Filed: November 17, 2003
    Publication date: July 21, 2005
    Applicant: ARM Limited
    Inventors: Simon Watt, Christopher Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Brochier, David Mansell, Jonathan Callan
  • Publication number: 20050114616
    Abstract: A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request.
    Type: Application
    Filed: September 3, 2004
    Publication date: May 26, 2005
    Applicant: ARM LIMITED
    Inventors: Andrew Tune, Peter Aldworth, Simon Watt, Lionel Belnet, David Mansell
  • Publication number: 20040177261
    Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Application
    Filed: November 17, 2003
    Publication date: September 9, 2004
    Inventors: Simon Charles Watt, Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton