Abstract: Phase discrimination and data separation method and apparatus for on-track error recovery by shifting input data in time relative to a clock to improve recovery of error bits due to bit shift in a disk storage system having a servo clock syncronized to a disk's rotational speed and a refernce clock which must be synchronized to the servo clock to insure that the data previously written onto the disk will be retrieved correctly during read back. Data encoded in (1,7) or denser codes can be recovered because of fewer transitions in a phase discriminator and therefore a shortened phase discrimination cycle in a feedback loop to avoid interference into the following correction. Readback data pulses for address mark (AM) search operations are standardized while a PLL is phase locked to the servo data, reducing or eliminating misdetection of AM due to delay skew or pulse width variations. Sequential logic avoids race conditions.

Abstract: A pulse signal conditioner filters and equalizes signal pulses representing digital data whether or not obtained from a magnetic recording device. Modified low pass filters filter the pulse signals and also derive and feed forward the second time derivative of the filtered pulse signals. The filtered pulse and the second time derivative thereof are combined to slim the pulse. Further slimming is provided by delay line equalizers having three paths. A first path for attenuating the pulse signals, a second path for delaying the pulse signals for a first delay, and a third path for delaying the pulse signals for a second delay and attenuation. Pulse signals from the three paths are combined to further slim the pulse.

Abstract: A data detection system and method for a bubble memory is disclosed in which the memory is operated in a start-stop mode during reading of data stored in two separate major loops which are stepped concurrently and wherein each major loop comprises interleaved data and no-data cells. The field rotation is controlled so that if the read operation is stopped, a no-bubble cell of each major loop is stopped adjacent the magneto-resistive sensor which provides read data signals to the detector of that major loop. The detector involves a detection cycle comprising a reference portion and a data portion. The signal generated during the data portion is integrated and compared against the integrated value of the signal generated during the previous reference portion. The comparison of two integrated values, one from a data cell and one from a reference cell, produces different results depending on whether a bubble or no-bubble was stored in the data cell.

Abstract: This current switch driving circuit arrangement particularly for, but not necessarily limited to, inductive device current switching, comprises a pair of output transistors constituting a driving transistor for turning ON a subsequent switching transistor and a current sinking transistor for turning OFF that switching transistor. A receiver circuit is arranged for applying one bilevel logical signal for alternatively driving the two transistors by way of intermediate circuits each having current multiplying circuitry for deriving the necessary driving currents. The intermediate circuitry is effective for toggling the current from one of the transistors to the other with provisions for insuring speedy switching action.