Abstract: A method or sensor arrangement for providing capacitive sensor detection with at least one capacitive sensor comprises a transmitting electrode and a receiving electrode. A stimulus at the transmitting electrode is generated and a signal is received from the receiving electrode and data packets are generated, each packet comprising a plurality of samples. The plurality of samples are weighted by providing less gain at a beginning and end of each packet with respect to a center of each packet; and the weighted samples are integrated to generate an output signal for each packet.

Abstract: An input device has one or more electrodes configured for capacitive sensing, an electronic circuit, one or more conductive feed line(s) connecting the one or more electrode(s) with the electronic circuit, wherein the device is configured to increase or decrease a signal received from at least one of the electrodes through an associated feed line in function of at least one other signal from another electrode.

Abstract: A sensor system has an acquisition unit comprising an analog to digital converter generating a series of digital sensor signals, a first evaluation unit receiving the series of digital sensor signals for evaluation, wherein the first evaluation unit generates output signals that correspond to a sensor event, and a second evaluation unit independent from said first evaluation unit receiving the series of digital sensor signals. At least a first and second series of digital sensor signals is processed by the second evaluation unit to generate a control signal that is configured to select a sampling frequency controlling the analog-to-digital converter, wherein the first and second series of digital sensor signals are sampled at different sampling frequencies.

Abstract: An input device has one or more electrodes configured for capacitive sensing, an electronic circuit, one or more conductive feed line(s) connecting the one or more electrode(s) with the electronic circuit, wherein the device is configured to increase or decrease a signal received from at least one of the electrodes through an associated feed line in function of at least one other signal from another electrode.

Abstract: A sensor system has an acquisition unit comprising an analog to digital converter generating a series of digital sensor signals, a first evaluation unit receiving the series of digital sensor signals for evaluation, wherein the first evaluation unit generates output signals that correspond to a sensor event, and a second evaluation unit independent from said first evaluation unit receiving the series of digital sensor signals. At least a first and second series of digital sensor signals is processed by the second evaluation unit to generate a control signal that is configured to select a sampling frequency controlling the analog-to-digital converter, wherein the first and second series of digital sensor signals are sampled at different sampling frequencies.

Abstract: An input device has one or more electrodes configured for capacitive sensing, an electronic circuit, one or more conductive feed line(s) connecting the one or more electrode(s) with the electronic circuit, wherein the device is configured to increase or decrease a signal received from at least one of the electrodes through an associated feed line in function of at least one other signal from another electrode.

Abstract: A method or sensor arrangement for providing capacitive sensor detection with at least one capacitive sensor comprises a transmitting electrode and a receiving electrode. A stimulus at the transmitting electrode is generated and a signal is received from the receiving electrode and data packets are generated, each packet comprising a plurality of samples. The plurality of samples are weighted by providing less gain at a beginning and end of each packet with respect to a center of each packet; and the weighted samples are integrated to generate an output signal for each packet.

Abstract: An input device has one or more electrodes configured for capacitive sensing, an electronic circuit, one or more conductive feed line(s) connecting the one or more electrode(s) with the electronic circuit, wherein the device is configured to increase or decrease a signal received from at least one of the electrodes through an associated feed line in function of at least one other signal from another electrode.

Abstract: A device for detecting and quantifying an unbalance between first and second electric paths (R, S; S, VPS), particularly for a touch detection system, comprises: (a) comparison means (CC; CD) receiving at respective inputs the first and second paths; (b) variable transfer capacitance means (CPB; CPC) connected to at least one of the paths; and (c) a control unit (UC) connected between the comparison means and the variable transfer capacitance means and adapted to vary the variable transfer capacitance of said variable transfer capacitance means as a function of the result (Q) produced by the comparison means up to compensation of the unbalance.

Abstract: A device for detecting and quantifying an unbalance between first and second electric paths (R, S; S, VPS), particularly for a touch detection system, comprises: (a) comparison means (CC; CD) receiving at respective inputs the first and second paths; (b) variable transfer capacitance means (CPB; CPC) connected to at least one of the paths; and (c) a control unit (UC) connected between the comparison means and the variable transfer capacitance means and adapted to vary the variable transfer capacitance of said variable transfer capacitance means as a function of the result (Q) produced by the comparison means up to compensation of the unbalance.

Abstract: In a reference current generator, a current mirror has a referent branch with a first current flowing thereon and a mirror branch to produce a second current by mirroring the first current, a first transistor is coupled to the referent branch, a second transistor is coupled to the mirror branch and has a gate coupled to the gate of the first transistor, one or more third transistors each produces a reference current by mirroring the first current or the second current to supply for a load, and a resistor having a resistance proportional to the absolute temperature is coupled to the first transistor such that a third current equal to the summation of the first current and all the mirrored reference currents flows through the resistor.

Abstract: A class AB operational buffer comprises an output stage, a voltage supply circuit to provide a first voltage and a second voltage to drive the output stage, a first current source to provide a first current, a second current source to provide a second current, a first current mirror having a first reference branch coupled with the first current and a first mirror branch coupled with the second current through the voltage supply circuit, and a second current mirror having a second reference branch coupled between the second current source and first mirror branch and a second mirror branch coupled between the first current source and first reference branch.

Abstract: In a reference current generator, a current mirror has a referent branch with a first current flowing thereon and a mirror branch to produce a second current by mirroring the first current, a first transistor is coupled to the referent branch, a second transistor is coupled to the mirror branch and has a gate coupled to the gate of the first transistor, one or more third transistors each produces a reference current by mirroring the first current or the second current to supply for a load, and a resistor having a resistance proportional to the absolute temperature is coupled to the first transistor such that a third current equal to the summation of the first current and all the mirrored reference currents flows through the resistor.

Abstract: A class AB operational buffer comprises an output stage, a voltage supply circuit to provide a first voltage and a second voltage to drive the output stage, a first current source to provide a first current, a second current source to provide a second current, a first current mirror having a first reference branch coupled with the first current and a first mirror branch coupled with the second current through the voltage supply circuit, and a second current mirror having a second reference branch coupled between the second current source and first mirror branch and a second mirror branch coupled between the first current source and first reference branch.

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.