Patents by Inventor Lionel Riviere-Cazaux

Lionel Riviere-Cazaux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10796056
    Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory A. Northrop, Lionel Riviere-Cazaux, Lars Liebmann, Kai Sun, Norihito Nakamoto
  • Publication number: 20190392106
    Abstract: Original cell design rule violations with respect to a second wiring layer are identified, while conductors of the second wiring layer are in an original position. The conductors of the second wiring layer are offset into different offset positions, and then the process of identifying violations is repeated for each of the offset positions. With this, metrics are generated for the original cell for the original position and each of the offset positions. Then, the original cell or the pitch of the second wiring layer are altered to produce alterations. The processes of identifying violations, offsetting conductors in the second wiring layer, repeating the identification of violations for all offsets, and generating metrics are repeated for each of the alterations. The original cell or one of the alterations is then selected, based on which cell produces the lowest number of violations of the design rules.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Gregory A. Northrop, Lionel Riviere-Cazaux, Lars Liebmann, Kai Sun, Norihito Nakamoto
  • Patent number: 9842185
    Abstract: Methods and apparatuses for configuring group constraints of features of cells for a multi-patterning process are provided. The apparatus determines features within a circuit layout, distance constraints for at least one of the features, group constraints for the features based on the distance constraints, the group constraints defining limits on groups assignable to each of the features. In addition, the apparatus receives an integrated circuit layout including a plurality of abutting cells. The apparatus then determines whether group constraints of a second cell conflict with group constraints of a first cell, the second cell abutting with the first cell, and configures a subset of the group constraints of the second cell based on the group constraints of the first cell and based on the group constraints of the second cell that conflict with the group constraints of the first cell.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Lionel Riviere-Cazaux
  • Publication number: 20170053057
    Abstract: Methods and apparatuses for configuring group constraints of features of cells for a multi-patterning process are provided. The apparatus determines features within a circuit layout, distance constraints for at least one of the features, group constraints for the features based on the distance constraints, the group constraints defining limits on groups assignable to each of the features. In addition, the apparatus receives an integrated circuit layout including a plurality of abutting cells. The apparatus then determines whether group constraints of a second cell conflict with group constraints of a first cell, the second cell abutting with the first cell, and configures a subset of the group constraints of the second cell based on the group constraints of the first cell and based on the group constraints of the second cell that conflict with the group constraints of the first cell.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventor: Lionel RIVIERE-CAZAUX
  • Patent number: 9566980
    Abstract: Systems, methods, and devices of the various embodiments enable masked priming stimuli to be provided to machine operators in advance of audible warnings issued by a safety warning system of a manned machine system when an emergency is imminent. In the various embodiments, the safety warning system of the manned machine system may output a masked priming stimulus in response to the machine operator performing a target action to teach a machine operator to take the target action associated with an emergency.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: February 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Lionel Riviere-Cazaux
  • Publication number: 20160257305
    Abstract: Systems, methods, and devices of the various embodiments enable masked priming stimuli to be provided to machine operators in advance of audible warnings issued by a safety warning system of a manned machine system when an emergency is imminent. In the various embodiments, the safety warning system of the manned machine system may output a masked priming stimulus in response to the machine operator performing a target action to teach a machine operator to take the target action associated with an emergency.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 8, 2016
    Inventor: Lionel Riviere-Cazaux
  • Patent number: 7735029
    Abstract: At a particular stage in design of an integrated circuit, DFM improvements are identified which might conflict with design requirements applicable during a subsequent stage in the design flow. These DFM improvements are “reserved” that is, they are not implemented right away. However, an instance of a DFM-optimized version of this portion of the design is generated, characterized and stored. Meta information is associated with the reserved DFM improvements, for example locations in the design which correspond to the reserved DFM improvements are tagged. If, after the subsequent stage in the design flow, processing of the meta-information (tags) shows that the reserved DFM improvement does not actually conflict with the potentially-conflicting design requirement, the corresponding reserved DFM improvement is implemented, for example, by swapping-in the stored instance of the DFM-optimized version of this portion of the design.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: June 8, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lionel Riviere-Cazaux
  • Publication number: 20080141047
    Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The method includes: receiving at least one activity related signal; determining a voltage level and a clock signal frequency to be provided to the system by applying a first policy for increasing the voltage level and clock signal frequency and a second policy for decreasing the voltage level and clock signal frequency, whereas the first policy differs from the second policy; and configuring a voltage source and a clock signal source in response to the determination.
    Type: Application
    Filed: September 10, 2004
    Publication date: June 12, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Lionel Riviere-Cazaux
  • Patent number: 6107745
    Abstract: A flat microtip display screen including a cathode provided with active areas of electron emission microtips; a cathodoluminescent anode provided, at least in front of the active microtip areas, with active areas of phosphor elements; a main grid of extraction of electrons emitted by the active microtips towards the phosphor elements; and on the cathode side, at least one sacrificial area of microtips adapted to being addressed, outside screen operation periods and independently from the active areas.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: August 22, 2000
    Assignee: Pixtech S.A.
    Inventors: Stephane Mougin, Lionel Riviere-Cazaux
  • Patent number: 5903108
    Abstract: The present invention relates to a flat display screen anode of the type including an active area having phosphor elements, the active area being surrounded with at least one track in a material having a secondary emission coefficient lower than or equal to one.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: May 11, 1999
    Assignee: Pixtech S.A.
    Inventors: Stephane Mougin, Francis Courreges, Bernard Bancal, Lionel Riviere-Cazaux