Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.

Abstract: Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects.

Abstract: A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.

Abstract: In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.

Abstract: In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.