Abstract: A method of operating a micromechanical device. The device is in a first state. Data for the next state of the device is loaded onto the activation circuitry of the device, where the next state may be the same state the device is currently in, or a state different from the first state. The equilibrium of the device is shifted away from the next state, by making the data appear complementary to the true data for the next state. When the trapping field is removed or lowered, and a signal to start the transition is provided, the device moves to its new state and the trapping field is reapplied. The data can be made to look complementary by either loading the complements to the true data, or by reversing the polarity of the trapping field.

Abstract: By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.

Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

Abstract: Proven data base is generated for electrical test responses of sporadic defects in integrated circuits as manufactured. Manufactured circuits are subjected to that electrical testing and resulting responses used to identify defect and check the manufacture to avoid its repetition.

Abstract: A semiconductor dynamic read/write memory device has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column address is latched when a serial mode is initiated, and the counter steps through the programmed number of bits, starting at the initial address. The number of bits used in the serial mode may be selected by metal-mask programming. To avoid a speed penalty, look-ahead circuitry initiates the set up for serial mode before the controls for this mode are detected.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled drive transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A processor system employs a self-refresh memory device which comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh address generator circuitry including an address counter or commutator and a multiplexer to insert the refresh address when a command is received or internally generated indicating a refresh cycle. If a refresh command is not being executed, the device is accessed by the processor in the usual manner if a memory address is received.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A random access read/write MOS memory device or the like employs a delay circuit in clock generators to produce small increments of delay. The delay circuit consists of a field effect transistor connected as a transfer device with its gate precharged and the gate-to-source capacitance much larger than the parasitics of the gate node. A larger transistor may be connected to the output node to improve the output waveform by holding down the output voltage at the beginning of a cycle.

Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.

Abstract: A random access read/write MOS memory device or the like employs a clock driver circuit which includes a push-pull type output stage with two transistors having a clock .PHI. and its complement .PHI. as gate inputs. An output node is pulled to a full supply voltage level by a pump transistor connecting the output node to the supply and having a delayed clock coupled to its gate. Another transistor with the supply voltage on its gate connects the output node to the gate of the pump transistor.

Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh address generator circuitry including an address counter or commutator and a multiplexer to insert the refresh address when a command is received or internally generated indicating a refresh cycle. If a refresh command is not being executed, the device is accessed in the usual manner if a memory address is received.

Abstract: A decoder for address inputs to a semiconductor memory or the like comprises a NOR gate having a number of parallel input transistors corresponding to the number of address bits to be decoded. The address bits and their complements are selectively connected to the gates of the input transistors and the sources of these transistors, rather than only to the gates as in prior decoders. The layout of this decoder more nearly matches the pitch of rows in a high density dynamic RAM.

Abstract: A semiconductor memory device of the MOS/LSI type using dynamic one-transistor cells has a serial input/output system. A serial shift register having a number of stages equal to the number of columns in the memory cell array is connected to the columns by transfer gates. The bits in the register may be loaded into the columns of the array and thus to an addressed row of cells, or data in one entire addressed row of cells may be loaded into the shift register stages via the columns and transfer gates. Data from external is loaded serially into the shift register for a write operation, or serially shifted out of the register to external for a read operation. The cell array can be addressed for refresh during the time that data is being shifted into or out of the serial register.

Abstract: A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.

Abstract: A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.