Abstract: An integrated circuit includes: one or more protected circuits; a license control circuit configured to request, from a license issuer, a license for activating the one or more protected circuits, the license request having a seed value; and a cryptographic circuit configured to verify the authenticity of a license received from the license issuer based on the seed value, wherein the license control circuit is configured to impose a validity limit on the received license, and to request a new license from the license issuer before the validity limit of the received license.

Abstract: The invention relates to a license-verification circuit for selectively activating one or more protected circuits (206) of a device (102) the license-verification circuit being capable of: deducing a device key from an identifier associated with the device (102); receiving a first license; decrypting the first license using the device key in order to extract a first verification code activating a first protected circuit by loading an activation code in an activation log (212) associated with the first protected circuit on the basis of a verification of the first verification code.

Abstract: An integrated circuit includes: one or more protected circuits; a license control circuit configured to request, from a license issuer, a license for activating the one or more protected circuits, the license request having a seed value; and a cryptographic circuit configured to verify the authenticity of a license received from the license issuer based on the seed value, wherein the license control circuit is configured to impose a validity limit on the received license, and to request a new license from the license issuer before the validity limit of the received license.

Abstract: The present disclosure generally relates to methods and devices for determining the attitude of a spacecraft by capturing a photograph of a starry sky, determining at least one potential star from the photograph, extracting for at least one potential star a spot pattern based upon rings having a similar area, searching a database for selecting a list of best candidate stars, verifying if the spot may be positively identified as a reference star by matching the spot with best candidate reference stars from a database, positively identifying at least one potential star, and determining the attitude of the spacecraft based upon at least one positively identified star.

Abstract: The invention relates to a license-verification circuit for selectively activating one or more protected circuits (206) of a device (102) the license-verification circuit being capable of: deducing a device key from an identifier associated with the device (102); receiving a first license; decrypting the first license using the device key in order to extract a first verification code activating a first protected circuit by loading an activation code in an activation log (212) associated with the first protected circuit on the basis of a verification of the first verification code.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.

Abstract: A memory device includes at least one memory cell having a first transistor coupled between a first storage node and a first supply voltage; a second transistor coupled between a second storage node and the first supply voltage and a single resistance switching element. Control terminals of the first and second transistors are coupled to the second and first storage nodes respectively. The single resistive switching element is coupled in series with the first transistor and is programmable to have one of first and second resistances. The first storage node is coupled to a first access line via a third transistor connected to said first storage node, and the second storage node is coupled to a second access line via a fourth transistor connected to the second storage node.

Abstract: The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.

Abstract: The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.

Abstract: The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, control terminals of the first and second transistors being coupled to the second and first storage nodes respectively; and a single resistance switching element (202), wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (Rmin, Rmax), wherein said first storage node is coupled to a first access line (BL) via a third transistor (110, 810) connected to said first storage node, and said second storage node is coupled to a second access line (BLB) via a fourth transistor (112, 812) connected to said second storage node.

Abstract: A logical calculation architecture including a multiplicity of configurable calculation components; a multiplicity of interconnection components; a first set of signals that configure the architecture by connecting between the calculation components and the interconnection components; a processor that generates the first set of configuration signals; a multiplicity of configurable control components, each control component connected to one of the calculation components and the control components generating at least one calculation instruction for calculation components; and a second set of signals that configure the control components.