Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

Abstract: A low-dropout regulator includes a power stage having an output terminal coupled to a load circuit operable in different operating modes in which it receives different output currents. An error amplifier has a first input coupled to a reference voltage and an output coupled to an input terminal of the power stage. A compensation circuit includes a first stage with an RC filter coupled to the input terminal of the power stage, and generating an initial compensation voltage. A second stage includes a first transistor coupled between a supply voltage and a second node, and controlled by a complementary control signal, a high-side capacitor coupled between the second node and ground, and a third transistor coupled between the initial compensation voltage and the second node, and controlled by a control signal representative of the current operating mode of the load circuit.

Abstract: In accordance with an embodiment, a connector is mechanically configurable between a wireless radio frequency transmission and a wired radio frequency transmission via a cylindrical dielectric radio frequency waveguide. The connector includes: a first package assembled to a printed circuit board provided with a radio frequency antenna; and a second package configured to be assembled to the waveguide, wherein the second package is configured to be removably assembled to the first package in the wired radio frequency transmission configuration and is separated from the first package in the wireless radio frequency transmission configuration.

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

Abstract: In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

Abstract: In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.

Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Abstract: A low-dropout regulator includes a power stage having an output terminal coupled to a load circuit operable in different operating modes in which it receives different output currents. An error amplifier has a first input coupled to a reference voltage and an output coupled to an input terminal of the power stage. A compensation circuit includes a first stage with an RC filter coupled to the input terminal of the power stage, and generating an initial compensation voltage. A second stage includes a first transistor coupled between a supply voltage and a second node, and controlled by a complementary control signal, a high-side capacitor coupled between the second node and ground, and a third transistor coupled between the initial compensation voltage and the second node, and controlled by a control signal representative of the current operating mode of the load circuit.

Abstract: A low-dropout voltage regulation device includes a power stage having an output terminal coupled to a load circuit, the load circuit being operable in a plurality of operating modes. The load circuit is configured to receive a different respective output current when in each of the plurality of operating modes. An error amplifier has an output coupled to an input terminal of the power stage. A compensation circuit is coupled to the input terminal of the power stage and is operable in a plurality of selectable configurations that are respectively tailored to the plurality of operating modes. The plurality of selectable configurations are selectable in response to a control signal representative of a current operating mode of the load circuit.

Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Abstract: An electronic envelope detection circuit includes an input signal detecting circuit having at least one MOS transistor configured to receive a radiofrequency input signal and to deliver an internal signal on the basis of the input signal. The biasing point of the at least one transistor is controlled by the input signal and a control signal. A processing circuit that is coupled to the input signal detecting circuit is configured to deliver a low-frequency output signal on the basis of the internal signal and further deliver the control signal on the basis of the output signal. In operation, the value of the control signal decreases when the average power of the input signal increases, and vice versa.

Abstract: A low-dropout voltage regulation device includes a power stage having an output terminal coupled to a load circuit, the load circuit being operable in a plurality of operating modes. The load circuit is configured to receive a different respective output current when in each of the plurality of operating modes. An error amplifier has an output coupled to an input terminal of the power stage. A compensation circuit is coupled to the input terminal of the power stage and is operable in a plurality of selectable configurations that are respectively tailored to the plurality of operating modes. The plurality of selectable configurations are selectable in response to a control signal representative of a current operating mode of the load circuit.

Abstract: A radiofrequency (RF) amplifier includes an input terminal, an output terminal, and a power supply and biasing stage having an output coupled to the input terminal. An amplification stage of the RF amplifier includes a first transistor having a control terminal coupled to the input terminal and a first conduction terminal coupled to the output terminal. The power supply and biasing stage is configured to generate a bias voltage at the control terminal of the first transistor to simultaneously regulate a power supply voltage of the amplification stage to a first voltage and a bias current of the amplification stage to a first current.

Abstract: A radiofrequency (RF) amplifier includes an input terminal, an output terminal, and a power supply and biasing stage having an output coupled to the input terminal. An amplification stage of the RF amplifier includes a first transistor having a control terminal coupled to the input terminal and a first conduction terminal coupled to the output terminal. The power supply and biasing stage is configured to generate a bias voltage at the control terminal of the first transistor to simultaneously regulate a power supply voltage of the amplification stage to a first voltage and a bias current of the amplification stage to a first current.

Abstract: An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.

Abstract: An amplifier includes at least two amplification stages coupled in parallel. Each amplification stage includes at differential pair of amplifying MOS transistors having gates connected to a first and second input nodes common to amplifying stages, and bulk regions connected to each other but insulated from bulk regions of the amplifying MOS transistors of the other amplification stages. A configuration circuit generates bias voltage for application to the bulk terminals in each amplification stage to set the threshold voltages of the amplifying MOS transistors, and thus configuring the operating range of each amplification stage so that different amplification stages have different operating ranges.

Abstract: A phase interpolator receiving a first signal having an oscillation frequency Fin and providing a second signal having said oscillation frequency and having a phase shift ?? with respect to the first signal which depends on a third signal. The interpolator includes a variable phase-shifter receiving the first signal and providing the second signal, the phase-shifter circuit includes an oscillator having a variable natural frequency Fo controlled by a fourth signal; a phase comparator capable of receiving the first and second signals and of providing a fifth signal representative of said phase shift; and a unit capable of providing the fourth signal which depends on the third and fifth signals.

Abstract: A method of analog-to-digital conversion over n bits of an analog signal, including the steps of: comparing the amplitude of the analog signal with a threshold representing the amplitude of the full-scale analog signal divided by 2k, where k is an integer smaller than n; performing an analog-to-digital conversion of the analog signal over n?k bits to obtain the n?k most significant bits of a binary word over n bits if the result of the comparison step indicates that the amplitude of the input signal is greater than the threshold, and the n?k least significant bits of this binary word otherwise. An analog-to-digital converter and its application to image sensors.