Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

Abstract: High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

Abstract: Systems and methods for essentially continuous audio flow for Internet of Things (IoT) devices during power mode transitions contemplate an audio bus, such as a SOUNDWIRE audio bus, to maintain an audio stream during a clock transition without having to tear down the audio stream as a new clock becomes active on the audio bus. By preserving the audio stream during such a transition, gaps in the audio are avoided resulting in better performance and end user experience.

Abstract: Systems and methods for essentially continuous audio flow for Internet of Things (IoT) devices during power mode transitions contemplate an audio bus, such as a SOUNDWIRE audio bus, to maintain an audio stream during a clock transition without having to tear down the audio stream as a new clock becomes active on the audio bus. By preserving the audio stream during such a transition, gaps in the audio are avoided resulting in better performance and end user experience.

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

Abstract: Tunneling over Universal Serial Bus (USB) sideband channel systems and methods provide a way to tunnel I2C transactions between a master and slaves over USB 4.0 sideband channels. More particularly, a slave address table lookup (SATL) circuit is added to a host circuit. Signals from an I2C bus are received at the host, and any address associated with a destination is translated by the SATL. The translated address is passed to a low-speed interface associated with a sideband channel in the host circuit. Signals received at the low-speed interface are likewise reverse translated in the SATL and then sent out through the I2C bus. In this fashion, low-speed I2C signals may be routed over the sideband channel through the low-speed sideband interface portion of the USB interface.

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. A feedback mechanism enables a transmitting device to identify the provider of feedback for a multicast transmission, and the feedback transmitted by one or more individual receivers of the multicast transmission. A method includes receiving a multicast write command from the serial bus in a first datagram, writing a data byte received in a first data frame of the first datagram to a register address identified by the first datagram, and providing device-specific feedback regarding the first datagram in a multibit slot within the second data frame. The multibit slot is one of a plurality of sequential multibit slots defined for the second data frame. Each multibit slot in the plurality of sequential multibit slots may provide device-specific feedback from one receiving device addressed by the multicast write command.

Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Abstract: In some aspects, the present disclosure provides a method for communicating audio data. In one example, the method includes determining whether a condition for each transport opportunity on an audio channel is met based on an audio sample rate and a channel rate of the audio channel. For each transport opportunity, upon determining that the condition is met for the transport opportunity, the method also includes transmitting audio sample data over the transport opportunity or receiving audio sample data at the transport opportunity.

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

Abstract: Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

Abstract: Multiple masters connecting to a single slave in an audio system designate a primary master between the multiple masters. Clock signals from secondary masters are turned off. In a first exemplary aspect, data signals from the secondary masters are still provided over distinct data lines to the slave. In a second exemplary aspect, data signals from the secondary masters are multiplexed onto a single data line of the primary master.

Abstract: Systems and methods for power conservation on an audio bus through clock manipulation allow a clock signal on an audio bus such as a SOUNDWIRE audio bus to be stopped when there are no pending commands from a master device. The clock signal may resume when a new command from the master device is generated or the master device receives an interrupt from a slave device.

Abstract: Systems and methods for multi-threshold sensing at an audio receiver, and systems and methods for calibrating an audio system to optimize for the specific configuration of the audio system are disclosed herein. In some implementations of a multi-threshold receiver, at least one additional voltage level is selected to trigger latching events within the receiver based on changes of the receiver input (which includes differential signals Vp and Vn) and in turn, to generate internal signals within the multi-threshold receiver, and then logic operations are performed on these internal signals to generate the output of the multi-threshold receiver.

Abstract: Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.