Abstract: An electronic device (22, 48, 50) includes an array (26) of memory cells, which are configured to store data values. One or more sense amplifiers (40) have respective inputs for receiving signals from the memory cells and are configured to output the data values corresponding to the received signals. Switching circuitry (36, 52) is coupled between the array of the memory cells and the sense amplifiers and is configured to receive an indication of a temporal pattern and to route the signals from the memory cells among the inputs of the sense amplifiers in accordance with the temporal pattern.

Abstract: A multi-die chip assembly is described, the multi-die chip assembly including at least one detection apparatus which detects manipulations of the multi-die chip assembly, the detection apparatus including a distributed circuit including a circuit whose elements are distributed among those dies which include the elements of a local reference circuit, the distributed circuit including a free running clock, at least one local reference circuit disposed in at least one die of the multi-die chip assembly, each of the local reference circuits including a free running clock, and at least one non-volatile memory, in which is stored during manufacture of the multi-die chip assembly, an allowed range of a result of a function having at least two arguments for each reference circuit a value of the frequency of the local reference circuit as manufactured, and a value of the frequency of the distributed circuit as manufactured, at least one element of the plurality of memories being disposed in each die including the elem

Abstract: An integrated circuit device (20, 60) includes a plurality of memory cells (22), which are configured to store data. Multiple P-N junctions (24) are arranged so that a single, respective P-N junction is disposed in proximity to each memory cell and is configured to emit optical radiation during readout from the memory cell with a wavelength matching an emission wavelength of the memory cell.

Abstract: A method for data transfer includes receiving a control signal triggering a transfer of a secret value into an element (24) of a circuit (20). In response to the control signal, a dummy value (42, 50) and the secret value are inserted in succession into the element of the circuit.

Abstract: An integrated circuit device (20, 60) includes a plurality of memory cells (22), which are configured to store data. Multiple P-N junctions (24) are arranged so that a single, respective P-N junction is disposed in proximity to each memory cell and is configured to emit optical radiation during readout from the memory cell with a wavelength matching an emission wavelength of the memory cell.

Abstract: An electronic device (22, 48, 50) includes an array (26) of memory cells, which are configured to store data values. One or more sense amplifiers (40) have respective inputs for receiving signals from the memory cells and are configured to output the data values corresponding to the received signals. Switching circuitry (36, 52) is coupled between the array of the memory cells and the sense amplifiers and is configured to receive an indication of a temporal pattern and to route the signals from the memory cells among the inputs of the sense amplifiers in accordance with the temporal pattern.

Abstract: An electronic device (22, 72) includes an array (24, 74) of memory cells, including at least one range of the cells in which at least one cell (38, 40, 76) is permanently fixed during manufacture of the device to have a given value, while others of the cells are permitted to be programmed subsequently. A readout circuit (26) is configured to concurrently read out all the cells in the range, including the at least one permanently-programmed cell and the subsequently-programmed cells.

Abstract: Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association with the noncompliant connectivity grid in either a first direction or a second direction, which can be substantially orthogonal to the first direction in some embodiments. The via caps are configured to provide each via with an amount of overlap area for sufficient coverage. In some instances, the method also includes forming a configuration layer for routing among a subset of the vias to provide at least the amount of overlap area for each via in the subset, and for forming the via caps for unrouted vias that are not part of the subset.

Abstract: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission.

Abstract: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission.

Abstract: Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, which, in turn, including circuit elements each having one or more inputs and one or more outputs. The cell also includes a configuration layer configured to form a logic device from one or more of the circuit elements. Further, the cell includes an interlayer connection layer configured to connect each of the inputs and the outputs to the configuration layer so as to enable each of the circuit elements to be independently accessible. Advantageously, the interlayer connection layer facilitates usage of each of the circuit elements to reduce the number of unused circuit elements in the cell.

Abstract: A method, computer readable medium apparatus and system for developing an Application-Specific Integrated Circuit (“ASIC”) are disclosed. In one embodiment, a method includes defining the functionality of a target ASIC device within a target system, as well as synthesizing circuits for the target ASIC device and a programmable logic device concurrently or nearly concurrently, thereby providing a conversion-less ASIC development flow using one or more programmable devices. In a specific embodiment, the conversion-less ASIC development flow requires no subsequent step of modifying a functional description for the target ASIC device from a functional description expressed in terms of the programmable logic device, thereby reducing an amount of time required to produce the target ASIC device.

Abstract: Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association with the noncompliant connectivity grid in either a first direction or a second direction, which can be substantially orthogonal to the first direction in some embodiments. The via caps are configured to provide each via with an amount of overlap area for sufficient coverage. In some instances, the method also includes forming a configuration layer for routing among a subset of the vias to provide at least the amount of overlap area for each via in the subset, and for forming the via caps for unrouted vias that are not part of the subset.

Abstract: Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, which, in turn, including circuit elements each having one or more inputs and one or more outputs. The cell also includes a configuration layer configured to form a logic device from one or more of the circuit elements. Further, the cell includes an interlayer connection layer configured to connect each of the inputs and the outputs to the configuration layer so as to enable each of the circuit elements to be independently accessible. Advantageously, the interlayer connection layer facilitates usage of each of the circuit elements to reduce the number of unused circuit elements in the cell.

Abstract: This invention discloses a cell forming part of a customizable logic array device, the cell including at least first (34) and second multiplexers, each having a select input and an output, at least two inverters (42, 52), each having an input and an output, and electrical connections (26, 54), selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the at least two inverters. A customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers is also disclosed. The invention additionally discloses a cell forming part of a customizable logic array device, the cell including a pair of identical logic portion located on opposite sides of a driver portion. The driver portion includes at least two drivers, each having an input and an output.

Abstract: This invention discloses a cell forming part of a customizable logic array device, the cell including at least first (34) and second multiplexers, each having a select input and an output, at least two inverters (42, 52), each having an input and an output, and electrical connections (26, 54), selectably connecting the output of the first multiplexer to either the select input of the second multiplexer or to the at least two inverters. A customizable logic array device including a plurality of cells, each cell including at least first and second multiplexers is also disclosed. The invention additionally discloses a cell forming part of a customizable logic array device, the cell including a pair of identical logic portion located on opposite sides of a driver portion. The driver portion includes at least two drivers, each having an input and an output.

Abstract: A customizable integrated circuit including a plurality of electrically conducting routing layers formed on a substrate for interconnecting a plurality of logic units formed on the substrate, including a first routing layer including a plurality of elongate conductors extending generally in a given direction, a second routing layer including a plurality of transversely extending conductors, each adapted for interconnecting a termination of one of the plurality of elongate conductors to a beginning of another one of the plurality of elongate conductors; and at least a third routing layer including a plurality of local routing conductors, a plurality of customizable connections, preferably arranged generally in at least one row, between pairs of the plurality of elongate conductors via individual ones of the plurality of transversely extending conductors and, preferably, customizable connections between individual ones of the plurality of elongate conductors and a plurality of individual ones of the local routi