Patents by Inventor Lior Avital

Lior Avital has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176705
    Abstract: Aspects of a storage device are provided for handling GBBs with defects between global interconnects and local word lines. The storage device includes a plurality of blocks each including a plurality of word lines, a plurality of interconnects within an interconnect set and between multiple ones of the blocks, volatile memory, and a controller. The controller determines a logical address pattern associated with the multiple ones of the blocks respectively including a program failure, determines whether the logical address pattern is associated with the interconnect set for the multiple ones of the blocks, determines a common word line associated with the program failures in the multiple ones of the blocks, un-marks these blocks as GBBs, and refrains from programming the common word line during respective program operations in the multiple ones of the blocks. Thus, blocks may be reclaimed, defective word line(s) isolated, and likelihood of read-only modes reduced.
    Type: Application
    Filed: July 7, 2023
    Publication date: May 30, 2024
    Inventors: Mahim Raj GUPTA, Ramkumar Subramanian, Piyush Girish Sagdeo, Lior Avital
  • Patent number: 11756637
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: September 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michael Ionin, Lior Avital, Tomer T. Eliash, Lola Grin, Alexander Bazarsky, Itay Busnach, Lior Bublil, Mahim Gupta
  • Publication number: 20210149800
    Abstract: A system and method for a power-cycle based read scrub of a memory device is provided. A controller stores an access counter which indicates a number of times a logical block address (LBA) has been accessed. When the LBA is accessed, the LBA counter is incremented. If the LBA counter indicates a count higher than a predetermined count, data stored in the LBA is duplicated and the duplicate data is stored as backup data. Subsequent access of the LBA will show that the LBA count is higher than the predetermined count, so the backup data will be accessed rather than the original LBA, thus preventing read-induced failure of the data which may be caused by further repeated access of the same LBA.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 20, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Lior Avital, Mrinal Kochar, Daniel Linnen, Rohit Sehgal
  • Patent number: 10699776
    Abstract: A method is provided that includes performing a post-write read operation on a block of memory cells that includes a select gate transistor, and based on results of the post-write read operation selectively performing a select gate maintenance operation on the select gate transistor.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lior Avital, Niles Yang
  • Publication number: 20200194061
    Abstract: A method is provided that includes performing a post-write read operation on a block of memory cells that includes a select gate transistor, and based on results of the post-write read operation selectively performing a select gate maintenance operation on the select gate transistor.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Western Digital Technologies, Inc.
    Inventors: Lior Avital, Niles Yang
  • Publication number: 20040098573
    Abstract: In a family of telecommunications modules or other circuit boards, driver software is divided into a core support package for initializing board components common to the family of circuit boards and one or more extended support packages specific to individual members of the family. This facilitates a reduction in the amount of programming effort needed across the family of circuit boards as the core support package need only be developed once for the family of boards rather than developing complete driver programs for each member of the family. The remaining programming effort can then be focused on the specialized subroutines. In addition, changes in hardware common to each member of the family can be accommodated by redeveloping only the core program. This need only occur once for the entire family, rather than once for each member of the family.
    Type: Application
    Filed: November 18, 2002
    Publication date: May 20, 2004
    Applicant: ADC Telecommunication Israel Ltd.
    Inventors: Tal Hassid, Lior Avital, Meir Katz
  • Publication number: 20040015741
    Abstract: A watchdog device is refreshed using either a hardware strobe or a software output as the refresh strobe. The hardware strobe is selected when the software output is undesirable as the refresh strobe. Undesirability includes the inability of the software output to reliably refresh the watchdog device or an unknown ability of the software output to reliably refresh the watchdog device.
    Type: Application
    Filed: July 17, 2002
    Publication date: January 22, 2004
    Applicant: ADC Telecommunications Israel Ltd.
    Inventors: Noam Ben-Moyal, Mor Moshe, Lior Avital, Amir Sharon
  • Publication number: 20030229707
    Abstract: A method of transferring data from a host system to a target system includes creating a data record for transmitting data to the target in which the record includes a starting address for loading a sequence of data into a memory of the target system, one or more error detection codes, and an uninterrupted sequence of data for loading sequentially into the memory.
    Type: Application
    Filed: June 6, 2002
    Publication date: December 11, 2003
    Applicant: ADC Telecommunications Israel Ltd.
    Inventors: Amir Sharon, Lior Avital, David Feldman