Abstract: A memory device to sense a content of a memory cell includes: a pair of bit-lines; a memory cell coupled between the bit-lines; and a sensing circuit. The sensing circuit has at least two inputs for receiving respective currents from a current conveyor, and senses, when operating in a sensing mode, a difference between output currents. The difference between the output currents represents a content of the memory cell. The sensing circuit includes an output for outputting an output signal that represents the content of the memory cell. The current conveyor isolates the sensing circuit from the bit-lines, when the current conveyor is operated in an isolation mode, and has at least two outputs for providing, to the sensing circuit, output currents representing bit-lines currents; and equalizing the output currents before the current conveyor starts to operate in a current conveying mode.

Abstract: A method for evaluating temperature is disclosed. The method includes setting a configuration of a configurable delay line out of multiple possible configurations, and delaying a first input signal by a temperature sensitive delay line, delaying a second input signal by the configurable delay line. The configurable delay line is less sensitive to temperature than the temperature sensitive delay line. The method also includes detecting, by a phase detector, a delay difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line, repeating the setting, delaying of the first input signal, delaying of the second input signal and detecting, until the delay difference is below a threshold, and evaluating the temperature of the temperature sensitive delay line in response to a configuration of the configurable delay line that results in the delay difference that is below the threshold.

Abstract: A memory device and a method for sensing a content of a memory cell.

Abstract: A method for evaluating temperature is disclosed. The method includes setting a configuration of a configurable delay line out of multiple possible configurations, and delaying a first input signal by a temperature sensitive delay line, delaying a second input signal by the configurable delay line. The configurable delay line is less sensitive to temperature than the temperature sensitive delay line. The method also includes detecting, by a phase detector, a delay difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the configurable delay line, repeating the setting, delaying of the first input signal, delaying of the second input signal and detecting, until the delay difference is below a threshold, and evaluating the temperature of the temperature sensitive delay line in response to a configuration of the configurable delay line that results in the delay difference that is below the threshold.

Abstract: A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the con

Abstract: A device having temperature evaluating capabilities, the device includes: (i) a temperature sensitive delay line that comprises multiple first type NMOS transistors and first type PMOS transistors; (ii) an configurable delay line that comprises second type NMOS transistors and second type PMOS transistors; wherein a process condition sensitivity of first type NMOS transistors and first type PMOS transistors substantially equals a process condition sensitivity of the second type NMOS transistors and second type PMOS transistors; wherein the configurable delay line is less sensitive to temperature than the temperature sensitive delay line; (iii) a phase detector, coupled to an output of the temperature sensitive delay line and to an output of the adjustable delay line, the phase detector is adapted to determine a difference between a delay introduced by the temperature sensitive delay line and a delay introduced by the adjustable delay line; and (iv) a controller, adapted to: (a) find a configuration of the con