Abstract: Selectively writing relevant bins directly to a controller's volatile memory (e.g., SRAM) based on a next-to-write address and writing the remaining bins to a host's volatile memory (e.g., DRAM or HMB), avoids the need for any additional reads from host's volatile memory and writes from controller's volatile memory. Avoiding the need for any additional reads from host's volatile memory, which has a slower access time than controller's volatile memory, improves exit latency from the boot and low-power-state exit flows. Prior to writing the parity bins to the controller or the host, the controller may store parity bins and/or the next-to-write address in non-volatile memory. The next-to-write address is then evaluated to determine whether a party bin is written to the controller's volatile memory or the host's volatile memory.

Abstract: Selectively writing relevant bins directly to a controller's volatile memory (e.g., SRAM) based on a next-to-write address and writing the remaining bins to a host's volatile memory (e.g., DRAM or HMB), avoids the need for any additional reads from host's volatile memory and writes from controller's volatile memory. Avoiding the need for any additional reads from host's volatile memory, which has a slower access time than controller's volatile memory, improves exit latency from the boot and low-power-state exit flows. Prior to writing the parity bins to the controller or the host, the controller may store parity bins and/or the next-to-write address in non-volatile memory. The next-to-write address is then evaluated to determine whether a party bin is written to the controller's volatile memory or the host's volatile memory.

Abstract: A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.

Abstract: A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.