Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.

Abstract: A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.

Abstract: A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.

Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.

Abstract: A programming circuitry for a resistor of a resistive random-access memory (ReRAM) is provided. The programming circuitry includes a current-limiting circuit; a current-terminating circuit including a current measurement circuit and a control circuit; and a voltage-limiting circuit, wherein the current-limiting circuit, the current-terminating circuit, and the voltage-limiting circuit operate in concert.

Abstract: A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.

Abstract: A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.

Abstract: A method and a system for DC-to-DC conversion are provided herein. The system may include a direct current to direct current (DC-to-DC) converter which may include at least one silicon-oxide-nitride-oxide-silicon (SONOS) device operable to perform voltage multiplication. The method may include directionally altering the threshold voltage of at least one silicon-oxide-nitride-oxide-silicon (SONOS) device, including applying a positive or negative voltage to at least a gate region of said at least one SONOS device thereby forcing electrons or holes from a channel region in said SONOS device to tunnel through an oxide layer (SiO), become trapped in silicon nitride (SiN), and accumulate proximate to a source region and/or a drain region in said at least one SONOS device, said accumulated electrons or holes altering the threshold voltage of said at least one SONOS device in a direction of said source or said drain region.