Abstract: A system comprises quantum control interconnect circuitry configured to receive a plurality of fixed-frequency signals, a variable-frequency signal, a quantum control pulse, a quantum element readout pulse, and a quantum element return pulse. The circuitry is operable to upconvert the quantum control pulse using the fixed-frequency signals. The circuitry is operable to upconvert the readout pulse using the variable-frequency signal. The circuitry is operable to downconvert the return pulse using the variable-frequency signal.

Abstract: Quantum algorithms are performed via a quantum computer, by generating a quantum control pulse in a quantum controller and transmitting the quantum control pulse to a quantum processor. The quantum control pulse interacts with a qubit in the quantum processor. Within the quantum controller, a pulse processor generates a plurality of raw pulses that are modified by a front end hardware module. During the normal operation of the quantum controller, samples of the raw and/or modified pulses may be selected and saved to memory. During a design for validation (DFV) mode, the proper operation of the quantum controller is determined according to a simulation of the quantum controller and the saved samples. The DFV mode may be performed in parallel with normal operation without affecting the resources of the quantum controller.

Abstract: A feedback controller is provided to generate a quantum feedback operation to control one or more ancilla qubits in a quantum error correcting code. The quantum feedback operation is based on the measurement of the one or more ancilla qubits. The feedback controller is operable to dynamically adjust a state discrimination according to previous measurements of the one or more ancilla qubits.

Abstract: A system comprises quantum control interconnect circuitry configured to receive a plurality of fixed-frequency signals, a variable-frequency signal, a quantum control pulse, a quantum element readout pulse, and a quantum element return pulse. The circuitry is operable to upconvert the quantum control pulse using the fixed-frequency signals. The circuitry is operable to upconvert the readout pulse using the variable-frequency signal. The circuitry is operable to downconvert the return pulse using the variable-frequency signal.

Abstract: A system comprises quantum control interconnect circuitry configured to receive a plurality of fixed-frequency signals, a variable-frequency signal, a quantum control pulse, a quantum element readout pulse, and a quantum element return pulse. The circuitry is operable to upconvert the quantum control pulse using the fixed-frequency signals. The circuitry is operable to upconvert the readout pulse using the variable-frequency signal. The circuitry is operable to downconvert the return pulse using the variable-frequency signal.

Abstract: A system comprises quantum control interconnect circuitry configured to receive a plurality of fixed-frequency signals, a variable-frequency signal, a quantum control pulse, a quantum element readout pulse, and a quantum element return pulse. The circuitry is operable to upconvert the quantum control pulse using the fixed-frequency signals. The circuitry is operable to upconvert the readout pulse using the variable-frequency signal. The circuitry is operable to downconvert the return pulse using the variable-frequency signal.

Abstract: A system comprises quantum control interconnect circuitry configured to receive a plurality of fixed-frequency signals, a variable-frequency signal, a quantum control pulse, a quantum element readout pulse, and a quantum element return pulse. The circuitry is operable to upconvert the quantum control pulse using the fixed-frequency signals. The circuitry is operable to upconvert the readout pulse using the variable-frequency signal. The circuitry is operable to downconvert the return pulse using the variable-frequency signal.

Abstract: A method for use in construction of an electronic device and a transistor structure are presented. The method comprising: providing one or more nanotubes grown on a surface of a first substrate; providing a desired electrode arrangement fabricated on a surface of a second substrate. The electrode arrangement comprises at least two elevated source and drain electrodes and one or more gate electrodes located in between said elevated source and drain electrodes. The method also comprises bringing the electrode arrangement on the second substrate to close proximity with the first substrate such that surfaces of the first and second substrates face each other; scanning said first substrate with said electrode arrangement and determining contact of electrodes of the electrode arrangement with a nanotube located on the first substrate; and detaching said nanotube from the first substrate to provide a transistor structure comprising an isolated nanotube between the source and drain electrodes.