Patents by Inventor Lior Horesh

Lior Horesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979309
    Abstract: A method includes computing a diffusion vector starting with a seed, querying nodes for connections, reweighting diffusion vector based on the degrees, sorting nodes based upon magnitude in the reweighted diffusion vector which is obtained through wave relaxation solution of a time-dependent initial value problem, detecting a community through a sweep over the nodes according to their rank, and selecting a prefix that minimizes or maximizes an objective function.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 7, 2024
    Assignee: International Business Machines Corporation
    Inventors: Haim Avron, Lior Horesh, Raya Horesh, Omer Tripp
  • Publication number: 20240135185
    Abstract: A method to determine data uncertainty is provided. The method receives a high dimensional data input and a corresponding data output. The method trains a variational autoencoder (VAE) with the high dimensional data input to learn a low dimensional latent space representation of the high dimensional data input. An encoder part of the VAE outputs a set of distributions of the high dimensional dataset in a latent space. The method samples new data samples in the latent space using the set of distributions outputs from the encoder part of the VAE. The method learns a polynomial chaos expansion to map the new data samples in the latent space to the corresponding data output to learn the set of distributions and their relation to perform estimation with high-dimensional dataset under uncertainty such as missing values by estimating the values using the set of distributions.
    Type: Application
    Filed: February 10, 2023
    Publication date: April 25, 2024
    Inventors: Shashanka Ubaru, Paz Fink Shustin, Lior Horesh, Vasileios Kalantzis, Haim Avron
  • Publication number: 20240111581
    Abstract: An example operation may include one or more of invoking, via an operating system, execution of a plurality of software programs having a first mode of operation that causes the plurality of software programs to operate in a first resource consuming mode, monitoring physical resources of a computing device that are consumed by the plurality of software programs, determining to reduce or allow expanded consumption of the physical resources of the computing device by the plurality of software programs based on the monitored physical resources, and in response to the determination, switching from a first mode of operation of a software program from among the plurality of software programs and to a second mode of operation of the software program that causes the software program to operate in a second resource consuming mode that consumes either less or more physical resources than the first resource consuming mode.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Jonathan Lenchner, Lior Horesh, Francesca Rossi
  • Patent number: 11948093
    Abstract: Techniques for generating and managing, including simulating and training, deep tensor neural networks are presented. A deep tensor neural network comprises a graph of nodes connected via weighted edges. A network management component (NMC) extracts features from tensor-formatted input data based on tensor-formatted parameters. NMC evolves tensor-formatted input data based on a defined tensor-tensor layer evolution rule, the network generating output data based on evolution of the tensor-formatted input data. The network is activated by non-linear activation functions, wherein the weighted edges and non-linear activation functions operate, based on tensor-tensor functions, to evolve tensor-formatted input data. NMC trains the network based on tensor-formatted training data, comparing output training data output from the network to simulated output data, based on a defined loss function, to determine an update.
    Type: Grant
    Filed: October 5, 2022
    Date of Patent: April 2, 2024
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, TRUSTEES OF TUFTS COLLEGE, RAMOT AT TEL-AVIV UNIVERSITY LTD.
    Inventors: Lior Horesh, Elizabeth Newman, Misha E. Kilmer, Haim Avron
  • Patent number: 11941442
    Abstract: An example operation may include one or more of invoking, via an operating system, execution of a plurality of software programs having a first mode of operation that causes the plurality of software programs to operate in a first resource consuming mode, monitoring physical resources of a computing device that are consumed by the plurality of software programs, determining to reduce or allow expanded consumption of the physical resources of the computing device by the plurality of software programs based on the monitored physical resources, and in response to the determination, switching from a first mode of operation of a software program from among the plurality of software programs and to a second mode of operation of the software program that causes the software program to operate in a second resource consuming mode that consumes either less or more physical resources than the first resource consuming mode.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Lenchner, Lior Horesh, Francesca Rossi
  • Publication number: 20240095515
    Abstract: Decentralized bilevel optimization techniques for personalized learning over a heterogenous network are provided. In one aspect, a decentralized learning system includes: a distributed machine learning network with multiple nodes, and datasets associated with the nodes; and a bilevel learning structure at each of the nodes for optimizing one or more features from each of the datasets using a decentralized bilevel optimization solver, while maintaining distinct features from each of the datasets. A method for decentralized learning is also provided.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 21, 2024
    Inventors: Songtao Lu, Xiaodong Cui, Mark S. Squillante, Brian E.D. Kingsbury, Lior Horesh
  • Patent number: 11934479
    Abstract: A method for performing sparse quantum Fourier transform computation includes defining a set of quantum circuits, each quantum circuit comprising a Hadamard gate and a single frequency rotation operator, said set of quantum circuits being equivalent to a quantum Fourier transform circuit. The method includes constructing a subset of said quantum circuits in a quantum processor, said quantum processor having a quantum representation of a classical distribution loaded into a quantum state of said quantum processor. The method includes executing said subset of said quantum circuits on said quantum state, and performing a measurement in a frequency basis to obtain a frequency distribution corresponding to said quantum state.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 19, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tal Kachman, Mark S. Squillante, Lior Horesh, Kenneth Lee Clarkson, John A. Gunnels, Ismail Yunus Akhalwaya, Jayram Thathachar
  • Patent number: 11907715
    Abstract: Techniques are provided to implement hardware accelerated application of preconditioners to solve linear equations. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode entries of a preconditioning matrix which is storable in the array of cells. When the preconditioning matrix is stored in the array of cells, the processor is configured to apply the preconditioning matrix to a plurality of residual vectors by executing a process which includes performing analog matrix-vector multiplication operations on the preconditioning matrix and respective ones of the plurality of residual vectors to generate a plurality of output vectors used in one or more subsequent operations.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Vasileios Kalantzis, Lior Horesh, Shashanka Ubaru
  • Publication number: 20240037304
    Abstract: An apparatus can include at least a controller, quantum hardware, and an interface. The controller can be configured to generate command signals. The quantum hardware can include at least a plurality of qubits. The interface can be connected to the controller and the quantum hardware, the interface being configured to control the quantum hardware based on the command signals to implement a quantum circuit configured to simulate a boundary operator that creates a mapping of boundaries of a given graph having nodes and edges. For example, the quantum circuit can be configured to simulate a boundary operator that creates a mapping of simplices of orders, e.g., of all orders, in a given simplicial complex. A method can include creating a boundary operator on a quantum computer, where a quantum circuit is built using Pauli spin operators.
    Type: Application
    Filed: July 13, 2022
    Publication date: February 1, 2024
    Inventors: Ismail Yunus Akhalwaya, Yang-Hui He, Lior Horesh, Vishnumohan Jejjala, William Kirby, Kugendran Naidoo, Shashanka Ubaru
  • Publication number: 20240028939
    Abstract: A quantum computer-implemented system, method, and computer program product for quantum topological domain analysis (QTDA). The QTDA method achieves an improved exponential speedup and depth complexity of O(n log(1/(??))) where n is the number of data points, ? is the error tolerance, ? is the smallest nonzero eigenvalue of the restricted Laplacian, and achieves quantum advantage on general classical data. The QTDA system and method efficiently realizes a combinatorial Laplacian as a sum of Pauli operators; performs a quantum rejection sampling and projection approach to build the relevant simplicial complex repeatedly and restrict the superposition to the simplices of a desired order in the complex; and estimates Betti numbers using a stochastic trace/rank estimation method that does not require Quantum Phase Estimation. The quantum circuit and QTDA method exhibits computational time and depth complexities for Betti number estimation up to an error tolerance ?.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 25, 2024
    Inventors: Ismail Yunus Akhalwaya, Shashanka Ubaru, Kenneth Lee Clarkson, Mark S. Squillante, Vasileios Kalantzis, Lior Horesh
  • Publication number: 20240022247
    Abstract: Systems and methods for performing pairwise checking of data points in a dataset are described. An apparatus or computing device can include a controller, quantum hardware, and an interface. The controller can be configured to generate a command signal. The quantum hardware can include a plurality of qubits. The interface can be connected to the controller and the quantum hardware. The interface can be configured to control the quantum hardware based on the command signal received from the controller to perform pairwise checking for every pair of data points in a dataset to identify a property relating to the data points. The data points can be represented by the plurality of qubits.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Shashanka Ubaru, Ismail Yunus Akhalwaya, Mark S. Squillante, Kenneth Lee Clarkson, Vasileios Kalantzis, Lior Horesh
  • Publication number: 20240020563
    Abstract: Systems and methods for operating quantum systems are described. A controller of a quantum system can generate a command signal. The quantum system can include quantum hardware having a plurality of qubits. An interface of the quantum system can control the quantum hardware based on the command signal to sample an input vector represented by the first set of qubits, where the input vector includes mixed states with different Hamming weights. The interface can control the quantum hardware to entangle the first set of qubits to the second set of qubits, where the second set of qubits represent a count of nonzero elements in the input vector. The interface can control the quantum hardware to generate an output vector based on the entanglement of the first set of qubits to the second set of qubits, where the output vector includes one or more states having a specific Hamming weight.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Ismail Yunus Akhalwaya, Shashanka Ubaru, Kenneth Lee Clarkson, Mark S. Squillante, Vasileios Kalantzis, Lior Horesh
  • Publication number: 20240020565
    Abstract: Systems and methods for operating a quantum system are described. A controller of a quantum system can generate a command signal. The quantum system can include quantum hardware having a plurality of qubits. An interface of the quantum system can control the quantum hardware based on the command signal received from the controller to determine a plurality of moments of a matrix using a random state vector represented by the plurality of qubits. The controller can be further configured to output the plurality of moments of the matrix to a computing device to estimate a trace of a matrix function based on one or more selected moments among the plurality of moments. The matrix function can be a function of the matrix.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Shashanka Ubaru, Ismail Yunus Akhalwaya, Kenneth Lee Clarkson, Mark S. Squillante, Vasileios Kalantzis, Lior Horesh
  • Publication number: 20240020564
    Abstract: Systems and methods for operating a quantum system are described. A controller of a quantum system can generate a command signal. The quantum system can include quantum hardware having a plurality of qubits. An interface of the quantum system can control the quantum hardware based on the command signal to generate a random state vector represented by the plurality of qubits. The random state vector can include a specific number of independent entries. The interface can control the quantum hardware to determine moments of a matrix based on the random state vector. The controller can be further configured to output the moments of the matrix to a computing device to estimate a trace of the matrix using the moments.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Shashanka Ubaru, Kenneth Lee Clarkson, Ismail Yunus Akhalwaya, Mark S. Squillante, Vasileios Kalantzis, Lior Horesh
  • Patent number: 11790033
    Abstract: A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vasileios Kalantzis, Shashanka Ubaru, Lior Horesh, Haim Avron, Oguzhan Murat Onen
  • Patent number: 11775721
    Abstract: Techniques and a system for quantum circuit decomposition by integer programming are provided. In one example, a system includes a quantum circuit decomposition component and a simulation component. The quantum circuit decomposition component generates graphical data for a quantum circuit that is indicative of a graphical representation of the quantum circuit. The graphical representation is formatted as a hypergraph. The simulation component simulates the quantum circuit based on the graphical data associated with the hypergraph.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: October 3, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giacomo Nannicini, John A. Gunnels, Lior Horesh, Edwin Peter Dawson Pednault
  • Publication number: 20230306276
    Abstract: Techniques for generating and managing, including simulating and training, deep tensor neural networks are presented. A deep tensor neural network comprises a graph of nodes connected via weighted edges. A network management component (NMC) extracts features from tensor-formatted input data based on tensor-formatted parameters. NMC evolves tensor-formatted input data based on a defined tensor-tensor layer evolution rule, the network generating output data based on evolution of the tensor-formatted input data. The network is activated by non-linear activation functions, wherein the weighted edges and non-linear activation functions operate, based on tensor-tensor functions, to evolve tensor-formatted input data. NMC trains the network based on tensor-formatted training data, comparing output training data output from the network to simulated output data, based on a defined loss function, to determine an update.
    Type: Application
    Filed: October 5, 2022
    Publication date: September 28, 2023
    Inventors: Lior Horesh, Elizabeth Newman, Misha E. Kilmer, Haim Avron
  • Patent number: 11741391
    Abstract: Systems, computer-implemented methods, and computer program products that can facilitate quantum topological classification are described. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a topological component that employs one or more quantum computing operations to identify one or more persistent homology features of a topological simplicial structure. The computer executable components can further comprise a topological classifier component that employs one or more machine learning models to classify the topological simplicial structure based on the one or more persistent homology features.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 29, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tal Kachman, Kenneth Lee Clarkson, Mark S. Squillante, Lior Horesh, Ismail Yunus Akhalwaya
  • Patent number: 11734384
    Abstract: A device solves for eigenvalues of a matrix system. The device performs a domain decomposition of a matrix system into non-overlapping subdomains and a reordering of matrices of the matrix system. An interface variable projection subspace associated with interface variables of an adjacency graph of the matrix system is created. The interface variables are related to nodes of the adjacency graph which are connected with nodes located in neighboring partitions. An internal variable projection subspace is created that is associated with internal variables of the adjacency graph of the matrix system, wherein the internal variables are related to nodes of the adjacency graph which are connected only to nodes located in the same partition. A projection matrix is built based on the interface variable projection subspace and the internal variable projection subspace. The device determines eigenvalues that solve a Raleigh-Ritz eigenvalue problem utilizing the projection matrix.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Vasileios Kalantzis, Lior Horesh
  • Publication number: 20230195457
    Abstract: Techniques are provided to implement hardware accelerated application of preconditioners to solve linear equations. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode entries of a preconditioning matrix which is storable in the array of cells. When the preconditioning matrix is stored in the array of cells, the processor is configured to apply the preconditioning matrix to a plurality of residual vectors by executing a process which includes performing analog matrix-vector multiplication operations on the preconditioning matrix and respective ones of the plurality of residual vectors to generate a plurality of output vectors used in one or more subsequent operations.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Vasileios Kalantzis, Lior Horesh, Shashanka Ubaru