Patents by Inventor Lior Kamran

Lior Kamran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220214812
    Abstract: Techniques for performing data transfers may include determining a first page of user data to be transferred from a source data storage system to a target data storage system, wherein the source data storage system has a source page size granularity denoting a first size of backend I/O operations on the source data storage system, wherein the target data storage system has a target page size granularity denoting a second size of backend I/O operations on the target data storage system; performing processing on the source data storage system that constructs a second page of user data that is the second size, wherein the second page of user data includes the first page of user data that is the first size and another page of user data that is the first size; and transferring the second page of user data from the source to the target data storage system.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 7, 2022
    Applicant: EMC IP Holding Company LLC
    Inventors: Amitai Alkalay, Lior Kamran, Vasu Subramanian
  • Publication number: 20220155968
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory, and is configured to monitor latencies associated with processing of input-output operations in a plurality of storage nodes of a distributed storage system, to detect an unbalanced condition between the storage nodes based at least in part on the monitored latencies, and responsive to the detected unbalanced condition, to adjust an assignment of slices of a logical address space of the distributed storage system to the storage nodes. Adjusting the assignment of slices of the logical address space of the distributed storage system to the storage nodes responsive to the detected unbalanced condition illustratively comprises increasing a number of the slices assigned to one or more of the storage nodes having relatively low latencies and decreasing a number of slices assigned to one or more of the storage nodes having relatively high latencies.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Inventors: Vladimir Shveidel, Lior Kamran
  • Publication number: 20220129164
    Abstract: A storage control system generates a striped storage volume in an array of data storage devices. The striped storage volume includes multiple stripe sets, each associated with a different stripe type, and each having stripes that are assigned the stripe type associated with the stripe set. The stripe type represents a block size of the stripes included in the stripe set. A background stripe defragmentation process is performed to defragment stripes in a target stripe set and generate empty stripes. The empty stripes generated by the background stripe defragmentation process are added into an empty stripe set of the striped storage volume. The empty stripes in the empty stripe set have unassigned stripe types. A stripe type is assigned to an empty stripe in the empty stripe which is selected for removal and inclusion in the stripe set associated with the stripe type assigned to the empty stripe.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 28, 2022
    Inventors: Vladimir Shveidel, Lior Kamran
  • Publication number: 20220131802
    Abstract: At least one processing device comprises a processor and a memory coupled to the processor. The at least one processing device is configured to implement adaptive flow control in conjunction with processing of input-output operations in a storage system. The adaptive flow control comprises a first feedback loop in which a window size defining an amount of concurrent processing of the input-output operations in the storage system is adjusted responsive to a measured latency for processing of one or more of the input-output operations. The adaptive flow control further comprises a second feedback loop in which at least one latency threshold used to control adjustment of the window size in the first feedback loop is adjusted. The at least one processing device illustratively comprises at least one processing core of a multi-core storage node of a distributed storage system.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Inventors: Vladimir Shveidel, Lior Kamran
  • Patent number: 11314416
    Abstract: A storage control system generates a striped storage volume in an array of data storage devices. The striped storage volume includes multiple stripe sets, each associated with a different stripe type, and each having stripes that are assigned the stripe type associated with the stripe set. The stripe type represents a block size of the stripes included in the stripe set. A background stripe defragmentation process is performed to defragment stripes in a target stripe set and generate empty stripes. The empty stripes generated by the background stripe defragmentation process are added into an empty stripe set of the striped storage volume. The empty stripes in the empty stripe set have unassigned stripe types. A stripe type is assigned to an empty stripe in the empty stripe which is selected for removal and inclusion in the stripe set associated with the stripe type assigned to the empty stripe.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: April 26, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Lior Kamran
  • Publication number: 20220121563
    Abstract: Techniques are provided for automated adaptive endurance tuning of solid-state storage media. For example, a storage control system tracks usage metrics associated with utilization of solid-state storage devices of a storage system, wherein the storage system comprises an amount of over-provisioned capacity allocated in the solid-state storage devices according to an over-provisioning factor. The storage control system determines a current endurance value of the data storage system based at least in part on the usage metrics, and compares the current endurance value to a target endurance value to determine if the current endurance value differs from the target endurance value.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Inventors: Lior Kamran, Amitai Alkalay
  • Publication number: 20220121484
    Abstract: A method of managing operation of a computing device is provided. The method includes (a) running a system scheduler that schedules execution of a first application and a second application on a central processing unit (CPU) core of the computing device; (b) while the first application is executing on the core, detecting, by the first application, a context-switch opportunity; and (c) issuing, by the first application in response to detecting the context-switch opportunity, a blocking operation that triggers the system scheduler to perform a rescheduling operation between the first and second applications on the CPU core. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: Lior Kamran, Amitai Alkalay, Liran Loya
  • Publication number: 20220121361
    Abstract: A storage system in one embodiment comprises a front-end device and a first storage node corresponding to the front-end device. The first storage node comprises a processor that is separate from the front-end device. The front-end device is configured to obtain a write operation that comprises at least a first block of data and to calculate a hash digest based at least in part on the first block of data. The front-end device is configured to provide the hash digest to the processor. The processor is configured to identify a first data page that comprises a second block of data that is a target for replacement by the first block of data and to identify a second storage node based at least in part on the first data page. The processor is configured to transmit the hash digest to the second storage node.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Inventors: Lior Kamran, Amitai Alkalay
  • Publication number: 20220121377
    Abstract: A storage system comprises a plurality of storage devices that are configured to store data pages. The data pages are distributed across the plurality of storage devices in a plurality of data stripes. A processing device of a storage controller is configured to identify a data stripe that corresponds to a given data page that was stored on a failed storage device and to provide an indication of the identified data stripe to a first storage device. A first processing device of the first storage device is configured to obtain data pages corresponding to the identified data stripe from at least one storage device other than the failed storage device and to perform a parity calculation based at least in part on the obtained data pages to rebuild the given data page. The rebuilt given data page is then stored on a third storage device.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Inventors: Lior Kamran, Amitai Alkalay
  • Publication number: 20220092008
    Abstract: A technique manages input/output(I/O)-critical tasks and background tasks within a computer device. The technique involves identifying tasks on the computer device as I/O-critical tasks and background tasks, accessing a ready task list that indicates any ready I/O-critical tasks and any ready background tasks, and based on the accessed ready task list, performing the tasks on the computer device. Such a technique enables the computer device to make better decisions that reduce I/O latencies while still efficiently utilizing central processing unit (CPU) cycles.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Lior Kamran, Amitai Alkalay
  • Patent number: 11262945
    Abstract: A method, computer program product, and computing system for defining one or more quality of service (QOS) classes for a storage system, wherein the storage system includes a storage processor communicatively coupled to one or more non-volatile memory express (NVMe) devices. One or more queues associated with each QOS class may be generated. One or more input/output (IO) operations associated with the one or more QOS classes may be processed on the one or more NVMe devices via the one or more queues associated with each QOS class.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 1, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Lior Kamran, Amitai Alkalay
  • Patent number: 11249800
    Abstract: A method, computer program product, and computing system for determining a block application execution utilization on a central processing unit (CPU) of the computing device. A non-block application execution utilization on the CPU may be determined. A CPU execution release interval and CPU execution release duration for the block application may be generated based upon, at least in part, the block application execution utilization and the non-block application execution utilization.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 15, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Lior Kamran, Vitaly Zharkov, Amitai Alkalay
  • Patent number: 11232010
    Abstract: A processing device monitors performance of a first thread of a first application executing on one of a plurality of processing cores of a storage system. The first thread comprises an internal scheduler controlling switching between a plurality of sub-threads of the first thread, and an external scheduler controlling release of the processing core by the first thread for use by at least a second thread of a second application different than the first application. In conjunction with monitoring the performance of the first thread in executing the first application, the processing device maintains a cumulative suspend time of the first thread over multiple suspensions of the first thread, with one or more of the multiple suspensions allowing at least the second thread of the second application to execute on the processing core, and generates performance measurements for sub-threads of the first thread using the cumulative suspend time.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: January 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Vladimir Kleiner
  • Publication number: 20210406066
    Abstract: At least one processing device comprises a processor and a memory coupled to the processor. The at least one processing device is configured to associate different classes of service with respective threads of one or more applications executing on at least one of a plurality of processing cores of a storage system, to configure different sets of prioritized thread queues for respective ones of the different classes of service, to enqueue particular ones of the threads associated with particular ones of the classes of service in corresponding ones of the prioritized thread queues, and to implement different dequeuing policies for selecting particular ones of the enqueued threads from the different sets of prioritized thread queues based at least in part on the different classes of service. The at least one processing device illustratively comprises at least a subset of the plurality of processing cores of the storage system.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Inventors: Vladimir Shveidel, Lior Kamran
  • Patent number: 11210141
    Abstract: A method, computer program product, and computing system for executing a first sub-thread of an operating system thread on a central processing unit (CPU) of the computing device. The CPU may be released for a defined period of time. One of an application and a second sub-thread of the operating system thread may be executed based upon, at least in part, an execution priority of the operating system thread and an execution priority of the application.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 28, 2021
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Lior Kamran, Amitai Alkalay
  • Publication number: 20210382777
    Abstract: At least one processing device is configured to detect a failure event impacting at least a first storage node of a plurality of storage nodes of a distributed storage system, and responsive to the detected failure event, to modify an input-output (IO) shaping mechanism in each of the storage nodes in order to at least temporarily reduce a total number of IO operations that are concurrently processed in the distributed storage system. For example, modifying an IO shaping mechanism in each of the storage nodes illustratively comprises transitioning the IO shaping mechanism in each of the storage nodes from a first operating mode to a second operating mode that is different than the first operating mode. The second operating mode of the IO shaping mechanism illustratively has a relatively faster responsiveness to changes in IO operation latency as compared to the first operating mode of the IO shaping mechanism.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Alex Soukhman, Lior Kamran
  • Publication number: 20210373773
    Abstract: A storage system in one embodiment comprises a front-end device and a plurality of storage nodes. A given storage node of the plurality of storage nodes comprises at least one processor and memory. The front-end device is configured to obtain a write operation comprising at least a first data page and to generate a content-based signature based at least in part on the first data page. The front-end device is further configured to compress the first data page and to generate first compression information corresponding to the first data page. The first compression information comprises an indication that the first data page has been compressed. The front-end device is further configured to provide the generated content-based signature, the compressed first data page and the first compression information to the given storage node.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Lior Kamran, Amitai Alkalay
  • Publication number: 20210357322
    Abstract: A storage system in one embodiment comprises storage nodes, an address space, address mapping sub-journals and write cache data sub-journals. Each address mapping sub-journal corresponds to a slice of the address space, is under control of one of the storage nodes and comprises update information corresponding to updates to an address mapping data structure. Each write cache data sub journal is under control of the one of the storage nodes and comprises data pages to be later destaged to the address space. A given storage node is configured to store write cache metadata in a given address mapping sub journal that is under control of the given storage node. The write cache metadata corresponds to a given data page stored in a given write cache data sub-journal that is also under control of the given storage node.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 18, 2021
    Inventors: Vladimir Shveidel, Lior Kamran
  • Publication number: 20210349762
    Abstract: A method, computer program product, and computing system for monitoring utilization of each central processing unit (CPU) core of a plurality of CPU cores. An average input/output (IO) latency for an operating system thread executing on the CPU core of the plurality of CPU cores may be determined. The operating system thread IO polling cadence for the at least one operating system thread executing on at least one CPU core may be adjusted based upon, at least in part, the utilization of each CPU core of the plurality of CPU cores and the average IO latency for the operating system thread executing on each CPU core of the plurality of CPU cores.
    Type: Application
    Filed: May 6, 2020
    Publication date: November 11, 2021
    Inventors: Lior Kamran, Amitai Alkalay
  • Patent number: 11163657
    Abstract: A method for use in a storage system, comprising: detecting that at least one storage device in a redundant storage device array has failed, the redundant storage device array including a plurality of storage devices; storing, in a memory, a recovery cache containing recovered data blocks, the recovered data blocks containing data previously stored on the failed storage device that has been calculated as part of executing read commands before the redundant storage device array is rebuilt; receiving an I/O command that is associated with the redundant storage device array, the I/O command including one of a read command or a write command; and executing the I/O command by using the recovery cache, wherein the redundant storage device array includes a plurality of storage regions, wherein any of the storage regions includes a respective portion of each of the plurality of storage devices.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Alex Soukhman