Patents by Inventor Lior Narkis
Lior Narkis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12218860Abstract: A network node includes a network adapter and a host. The network adapter is coupled to a communication network. The host includes a processor running a client process and a communication stack, and is configured to receive packets from the communication network, and classify the received packets into respective flows that are associated with respective chunks in a receive buffer, to distribute payloads of the received packets among the chunks so that payloads of packets classified to a given flow are stored in a given chunk assigned to the given flow, and to notify the communication stack of the payloads in the given chunk, for transferring the payloads in the given chunk to the client process.Type: GrantFiled: July 19, 2020Date of Patent: February 4, 2025Assignee: Mellanox Technologies, LtdInventors: Gal Yefet, Avi Urman, Gil Kremer, Lior Narkis, Boris Pismenny
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Publication number: 20250030649Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Inventors: Ortal Ben Moshe, Roee Moyal, Shay Aisman, Gil Bloch, Ariel Shahar, Roman Nudelman, Gil Kremer, Yossef Itigin, Lior Narkis
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Publication number: 20250028658Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.Type: ApplicationFiled: July 20, 2023Publication date: January 23, 2025Inventors: Ortal Ben Moshe, Roee Moyal, Shay Aisman, Gil Bloch, Ariel Shahar, Roman Nudelman, Gil Kremer, Yossef Itigin, Lior Narkis
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Publication number: 20240193106Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: ApplicationFiled: February 19, 2024Publication date: June 13, 2024Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
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Patent number: 11940933Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: GrantFiled: March 2, 2021Date of Patent: March 26, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
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Patent number: 11916790Abstract: A network adapter includes a host interface, a network interface, a memory and packet processing circuitry. The memory holds a shared buffer and multiple queues allocated to the multiple host processors. The packet processing circuitry is configured to receive from the network interface data packets destined to the host processors, to store payloads of at least some of the data packets in the shared buffer, to distribute headers of at least some of the data packets to the queues, to serve the data packets to the host processors by applying scheduling among the queues, to detect congestion in the data packets destined to a given host processor among the host processors, and, in response to the detected congestion, to mitigate the congestion in the data packets destined to the given host processor, while retaining uninterrupted processing of the data packets destined to the other host processors.Type: GrantFiled: May 4, 2020Date of Patent: February 27, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi Urman, Lior Narkis, Noam Bloch, Eyal Srebro, Shay Aisman
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Patent number: 11621920Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.Type: GrantFiled: September 4, 2022Date of Patent: April 4, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi Urman, Lior Narkis, Omri Kahalon
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Publication number: 20220417157Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.Type: ApplicationFiled: September 4, 2022Publication date: December 29, 2022Inventors: Avi Urman, Lior Narkis, Omri Kahalon
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Publication number: 20220407824Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry, and retrieve WRs from the multiple NSQs and execute data transmission operations specified in the WRs retrieved from the multiple NSQs.Type: ApplicationFiled: August 31, 2022Publication date: December 22, 2022Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
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Publication number: 20220377014Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Inventors: Avi Urman, Lior Narkis, Noam Bloch
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Patent number: 11476928Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.Type: GrantFiled: July 7, 2020Date of Patent: October 18, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Avi Urman, Lior Narkis, Liron Mula, Paraskevas Bakopoulos, Ariel Almog, Roee Moyal, Gal Yefet
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Patent number: 11470007Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.Type: GrantFiled: January 19, 2021Date of Patent: October 11, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi Urman, Lior Narkis, Omri Kahalon
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Patent number: 11451493Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.Type: GrantFiled: January 6, 2021Date of Patent: September 20, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
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Publication number: 20220283964Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.Type: ApplicationFiled: March 2, 2021Publication date: September 8, 2022Inventors: Idan Burstein, Dotan David Levi, Ariel Shahar, Lior Narkis, Igor Voks, Noam Bloch, Shay Aisman
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Patent number: 11438266Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.Type: GrantFiled: February 4, 2020Date of Patent: September 6, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Avi Urman, Lior Narkis, Noam Bloch
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Publication number: 20220231953Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to communicate with a host processor running multiple application programs. The processing circuitry includes one or more bandwidth-control policers, and is configured to receive from the communication network a packet destined to a given application program among the application programs running on the host processor, to associate a bandwidth-control policer with the packet, selected from among the bandwidth-control policers, and to apply the selected bandwidth-control policer to the packet to produce a policer result.Type: ApplicationFiled: January 19, 2021Publication date: July 21, 2022Inventors: Avi Urman, Lior Narkis, Omri Kahalon
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Patent number: 11388263Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.Type: GrantFiled: October 11, 2020Date of Patent: July 12, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dotan David Levi, Daniel Marcovitch, Lior Narkis, Avi Urman
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Publication number: 20220217101Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.Type: ApplicationFiled: January 6, 2021Publication date: July 7, 2022Inventors: Gal Yefet, Daniel Marcovitch, Roee Moyal, Ariel Shahar, Gil Bloch, Lior Narkis
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Patent number: 11323372Abstract: In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.Type: GrantFiled: April 21, 2020Date of Patent: May 3, 2022Assignee: MELLANOX TECHNOLOGIES LTD.Inventors: Avi Urman, Lior Narkis, Ariel Shahar
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Publication number: 20220116473Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.Type: ApplicationFiled: October 11, 2020Publication date: April 14, 2022Inventors: Dotan David Levi, Daniel Marcovitch, Lior Narkis, Avi Urman