Abstract: A probe for direct nano- and micro-scale electrical characterization of materials and semi conductor wafers. The probe (10) comprises a probe body (12), a first cantilever (20a) extending from the probe body. The first cantilever defining a first loop with respect to said probe body. The probe further comprises a first contact probe being supported by said first cantilever, and a second contact probe being electrically insulated from the first contact probe. The second contact probe being supported by the first cantilever or by a second cantilever (20b) extending from the probe body.

Abstract: A probe for direct nano- and micro-scale electrical characterization of materials and semi conductor wafers. The probe (10) comprises a probe body (12), a first cantilever (20a) extending from the probe body. The first cantilever defining a first loop with respect to said probe body. The probe further comprises a first contact probe being supported by said first cantilever, and a second contact probe being electrically insulated from the first contact probe. The second contact probe being supported by the first cantilever or by a second cantilever (20b) extending from the probe body.

Abstract: A multipoint probe for establishing an electrical connection between a test apparatus and a test sample, the multipoint probe comprising a base defining a top surface and a plurality of traces provided on the top surface, each trace individually interconnecting a contact pad and a contact electrode for establishing the electrical connection to the test sample, each trace comprising a wide portion connected to the contact pad and a narrow portion connected to the contact electrode; the first top surface comprising first intermediate surfaces, each interconnecting a pair of neighboring traces at their respective wide portions, and second intermediate surfaces, each interconnecting a pair of neighboring traces at their respective narrow portions, and the first intermediate surfaces being provided on a first level and the second intermediate surfaces being provided on a second level above the first level relative to the base.

Abstract: A multipoint probe for establishing an electrical connection between a test apparatus and a test sample, the multipoint probe comprising a base defining a top surface and a plurality of traces provided on the top surface, each trace individually interconnecting a contact pad and a contact electrode for establishing the electrical connection to the test sample, each trace comprising a wide portion connected to the contact pad and a narrow portion connected to the contact electrode; the first top surface comprising first intermediate surfaces, each interconnecting a pair of neighbouring traces at their respective wide portions, and second intermediate surfaces, each interconnecting a pair of neighbouring traces at their respective narrow portions, and the first intermediate surfaces being provided on a first level and the second intermediate surfaces being provided on a second level above the first level relative to the base.

Abstract: Non-planar via designs for sub-mounts on which to mount a LED or other optoelectronic device include a continuous layer of metal to conduct the current from the front-side (e.g., LED side) to the backside (e.g., SMD side) through the via and to provide a sufficiently stable and reliable under bump metallization for SMD soldering. Each UBM can be structured so that it does not fully cover the sidewall surfaces of the via that forms the front-to-backside interconnect. In some implementations, each via structure for the feedthrough metallization extends to a respective side-edge of the sub-mount.

Abstract: Non-planar via designs for sub-mounts on which to mount a LED or other optoelectronic device include a continuous layer of metal to conduct the current from the front-side (e.g., LED side) to the backside (e.g., SMD side) through the via and to provide a sufficiently stable and reliable under bump metallization for SMD soldering. Each UBM can be structured so that it does not fully cover the sidewall surfaces of the via that forms the front-to-backside interconnect. In some implementations, each via structure for the feedthrough metallization extends to a respective side-edge of the sub-mount.

Abstract: A submount for a micro-component includes a semiconductor substrate having a cavity defined in a front-side of the substrate in which to mount the micro-component. The submount also includes a thin silicon membrane portion at a bottom of the cavity and thicker frame portions adjacent to sidewalls of the cavity. The substrate includes an electrically conductive feed-through connection extending from a back-side of the substrate at least partially through the thicker silicon frame portion. Electrical contact between the feed-through connection and a conductive layer on a surface of the cavity is made at least partially through a sidewall of the cavity.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a preexisting semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: A method of fabricating a package with a light emitting device includes depositing a first metallization to form a conductive pad on which the light emitting device is to be mounted and to form one or more feed-through interconnections extending through a semiconductor material that supports the conductive pad. Subsequently, a second metallization is deposited to form a reflective surface for reflecting light, emitted by the light emitting device, through a lid of the package. Deposition of the second metallization is de-coupled from deposition of the first metallization.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a preexisting semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: Techniques are disclosed for fabricating a relatively thin package for housing a micro component, such as an opto-electronic or MEMs device. The packages may be fabricated in a wafer-level batch process. The package may include hermetically sealed feed-through electrical connections coupling the micro component to electrical contacts on an exterior surface of the package.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: A method of fabricating silicon micro-mirrors includes etching from opposite sides of a silicon wafer with a polished surface on at least one of the opposite sides, to form silicon bars each having a parallelogram-shaped cross-section and including a portion of the polished surface. At least one of the silicon bars is mounted on a mounting surface. The polished surface of the silicon bar may be used to reflect optical signals.

Abstract: A method of fabricating a package with a light emitting device includes depositing a first metallization to form a conductive pad on which the light emitting device is to be mounted and to form one or more feed-through interconnections extending through a semiconductor material that supports the conductive pad. Subsequently, a second metallization is deposited to form a reflective surface for reflecting light, emitted by the light emitting device, through a lid of the package. Deposition of the second metallization is de-coupled from deposition of the first metallization.

Abstract: A deformable spacer for wafer bonding applications is disclosed. The spacer may be used to keep wafers separated until desired conditions are achieved.

Abstract: Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.

Abstract: A package includes one or more optoelectronic components and a cap with an embedded glass window attached to a substrate. The optoelectronic component(s) is supported by the substrate and is capable of detecting or emitting light through the glass window. The glass window may serve as an optical filter. Techniques are disclosed for fabricating a relatively thin package with an embedded glass window in the cap.

Abstract: A method for accelerating or decelerating a moveable body which body is moved by urging a piezoelectric micromotor to the body in a first direction so that a contact region of the piezoelectric motor is pressed to the body and exciting vibrations in the piezoelectric micromotor at the contact region in the first direction and in a second direction along a direction of motion of the body, said vibrations having a first amplitude in the first direction and a second amplitude in the second direction, the method comprising: a) for acceleration, gradually changing a ratio between the second amplitude relative to the first amplitude from substantially zero to a desired non-zero value; or b) for deceleration, gradually changing the ratio between the second amplitude relative to the first amplitude from a non-zero value to substantially zero.