Abstract: Adjustable clock and power gating control is facilitated hereby. In aspects, a power management circuit is coupled to a memory controller circuit that is coupled to a memory resource circuit and to a plurality of heterogeneous client circuits configured to access the memory resource circuit via the memory controller circuit. The power management circuit is configured to receive operating parameters associated with the plurality of client circuits and to determine, based on the operating parameters, a threshold power state for the memory resource circuit. Additionally, the power management circuit is configured to initiate a clock gating operation, a power gating operation, or both for the memory resource circuit and to maintain at least the threshold power state for the memory resource circuit by limiting performance of the clock gating operation, the power gating operation, or both for the memory resource circuit. Other aspects and features are also claimed and described.

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to a plurality of networks of the computer system, which may include packet-switching capabilities. Such non-DRAM transactions may be routed via a virtual channel in some implementations. To facilitate handling of such transactions, the NSM gateway circuit may include dedicated routing storage (e.g., an input buffer for each source agent circuit on each of the plurality of networks and an output buffer for each destination agent circuit on each of the plurality of networks). The NSM gateway circuit may serve as a termination point for non-DRAM transactions within the computer system, allowing network credit for a message included in a non-DRAM transaction to be returned to a source agent circuit prior to delivery to one or more destination agent circuits.

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to first and second networks of the computer system. The NSM gateway circuit may route, for example, a message for a non-DRAM transaction from a source agent circuit coupled to the first network but not the second network to a destination agent circuit coupled to the second network but not the first network, and vice-versa. The NSM gateway circuit can also route messages for non-DRAM transactions between source and destination agent circuits both located on the same network. Still further, the NSM gateway circuit can route broadcast (i.e., one-to-many) transactions as well as network element configuration requests. In some implementations, a computer system may have multiple NSM gateway circuits, each assigned to handle non-DRAM transactions from an assigned set of agent circuits.

Abstract: An apparatus includes first agents configured to transfer transactions using an ordered protocol, as well as second agents configured to transfer transactions using a protocol with no enforced ordering. The apparatus may also include input/output (I/O) interfaces coupled to respective ones of the first agents and configured to enforce the ordered protocol. The apparatus may further include a communication network including a plurality of network switches. A particular one of the network switches may be coupled to at least one other network switch of the plurality. The apparatus may also include a network interface coupled to the second agents, to the I/O interfaces, and to the particular network switch. This network interface may be configured to transfer data transactions between the second agents and the particular network switch, and to transfer data transactions between the I/O interfaces and the particular network switch.

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Abstract: An integrated circuit (IC) configurable for use in one of a number of possible platforms is disclosed. The IC includes a number of different functional circuit blocks and a plurality of programmable register. The programmable registers, when programmed, can cause corresponding functional circuit blocks to be fully or partially disabled. The different platforms support different sets of peripherals. The IC is thus configured, using the programmable registers, for use in a particular platform to support its corresponding set of peripherals, while another instance of the IC may be configured for use in another platform, supporting its particular set of peripherals.

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Trigger logic circuits and rate control circuits may be implemented in combination with a power management circuit to control power provided to components of the integrated circuits. Power may be controlled based on receiving trigger signals from a power management unit. The power management circuit may implement power budgets for various components in the integrated circuits.

Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state.

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.