Abstract: A circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.

Abstract: One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.

Abstract: A clock data recovery circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.

Abstract: One embodiment relates to a lock detection circuit. The lock detection circuit includes at least a dither detection circuit and a lock filter. The dither detection circuit maintains a bi-directional count based on early and late signals from a sampler circuit and asserts a non-lock signal if the bi-directional count reaches either a positive non-lock assertion threshold or a negative non-lock assertion threshold. The lock filter increments a lock filter count for each sample and outputs a lock-initiated signal when the lock filter count reaches a pre-set maximum value. The maximum value of the lock filter count is greater than the non-lock assertion thresholds. Other embodiments and features are also disclosed.

Abstract: One embodiment relates to an interpolator-based clock and data recovery circuit which includes a de-multiplexer and a voting circuit. The de-multiplexer is arranged to de-multiplex a feedback signal from a sampler, and the voting circuit is arranged decimate the de-multiplexed feedback signal. The decimated feedback signal may be provided to a digital filter. Another embodiment relates to a method for clock and data recovery from a data signal. The method includes de-multiplexing and decimation of a feedback signal. Other embodiments and features are also disclosed.

Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract: A clock loss detection circuit is presented. The clock loss detection has two edge detection circuits and a clock loss detect counter circuit. Each edge detection circuit includes a reset signal circuit that generates a reset signal in response to a transition of a clock signal, and the reset signal circuit is connected to a clock input of the edge detection circuit. Each edge detection circuit also has a multiplexer connected to the reset signal circuit, and another multiplexer connected to the clock input. The clock loss detect counter circuit is connected to the edge detection circuits so that the clock loss detect counter circuit receives the reset signal from the second edge detection circuit and the clock signal from the first edge detection circuit.

Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract: A phase detector includes transistors that generate first and second phase error signals. The phase detector resets the first phase error signal in response to at least one of the first and the second phase error signals through a first reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the first reset path. The phase detector resets the second phase error signal in response to at least one of the first and the second phase error signals through a second reset path having a maximum reset delay that is equal to or less than a sum of switching delays of three transistors in the second reset path.