Abstract: A discrete element method contact model building method includes: selecting a filling body in a disaster-causing structure to obtain a change rule of cumulative loss of the filling body; performing test simulation, and determining a relation function of each group of corresponding mesoscopic mechanical parameters in each time period and mesoscopic parameters of a DEM contact model representing a change rule of macroscopical parameters of the filling body; embedding each mesoscopic parameter relation function into an existing particle contact model, performing test simulation, and updating a fracture failure criterion of the contact model according to a corresponding relation of macro-mesoscopic strength during model failure; and based on a seepage failure indoor test, building a seepage failure discrete element calculation model, and simulating the seepage failure process of a rock and soil mass by using the obtained particle contact model and the fracture criterion of the particle contact model.

Abstract: A lipid delivery system, a virus-like structure (VLS) vaccine constructed therefrom, and a lipid particle capable of encapsulating an mRNA molecule encoding a SARS-CoV-2-specific antigen are provided. After the lipid particle encapsulates an mRNA molecule encoding a SARS-CoV-2 antigen, a SARS-CoV-2 S1 antigen protein can be embedded on a surface of an envelope structure of the lipid under specific buffer conditions to produce a VLS vaccine with an antigen-encoding mRNA molecule encapsulated inside and an outer membrane presenting a required viral antigen protein. The vaccine has a superior specific antibody-inducing ability to a SARS-CoV-2 mRNA vaccine and a polypeptide vaccine, can maintain a long-lasting high antibody level, and can also exhibit excellent immune binding abilities for the emerging different variants.

Abstract: A recombinant antibacterial peptide TrSub, preparation method and application for the recombinant antibacterial peptide TrSub is disclosed, and belongs to the field of genetic engineering and biotechnology. The amino acid sequence of the recombinant antimicrobial peptide TrSub is shown in SEQ ID No. 1. The nucleotide sequence encoding the amino acid shown in SEQ ID NO.1 is shown in SEQ ID NO.2. The disclosure also provides a method for preparaing the recombinant antimicrobial peptide TrSub, wherein the recombinant antimicrobial peptide TrSub has an inhibitory effect on Escherichia coli, Salmonella, Staphylococcus aureus and Clostridium perfringens. The disclosure has good thermal stability, acid resistance, pepsin resistance and low hemolytic activity, and is beneficial to the application of the disclosure in the preparation of fee and feed additive.

Abstract: Aspects of the disclosure provide a method for linking input files during a linking process. The method includes receiving an input section that is to be mapped to a memory segment by a linker circuit, determining whether an out-of-memory (OOM) event occurs when an available memory space of the memory segment is unable to accommodate the input section, estimating a memory expansion size that would be required for the memory segment to be able to accommodate the input section when an OOM event occurs, and creating by the linker circuit a map file that includes the estimated memory expansion size of the memory segment.

Abstract: Aspects of the disclosure provide a method for identifying an induction variable in a loop during a compiling process. The method includes searching for a phi-function that includes a first operand and a second operand and defines a candidate basic induction variable (BIV), searching for an add/sub instruction that has a first register and a second register wherein the first register is the second operand of the phi-function, or the value in the first register is subsequently stored to the second operand of the phi-function through one or more move instructions, and determining the candidate BIV is a BIV when the second register of the add/sub instruction is the candidate BIV or stores a value that is passed from the candidate BIV through one or more move instructions.

Abstract: System and methods are provided for register allocation. An original code block and a target code block associated with a branch of an execution loop are determined. An original allocation of a plurality of physical registers to one or more original variables associated with the original code block is detected. A target allocation of the plurality of physical registers to one or more target variables associated with the target code block is determined. One or more temporary registers are selected from the plurality of physical registers based at least in part on the original allocation and the target allocation. The original allocation is changed to the target allocation using the selected temporary registers. Specifically, one or more instructions are generated to change the original allocation to the target allocation using the selected temporary registers. The instructions are executed using one or more processors.

Abstract: Aspects of the disclosure provide a method to support performance analysis. The method includes compiling bytecodes to generate native codes corresponding to the bytecodes in an electronic device, generating a file to include the bytecodes and the corresponding native codes in the file, collecting symbol information to map symbols in the bytecodes with offsets of corresponding native codes, and including the symbol information in the file to enable profiling.

Abstract: Aspects of the disclosure provide a method for code compilation. The method includes receiving instructions of a loop code for compiling, allocating one or more registers to variables before compiling the instructions into a loop body for the loop code, and compiling the instructions into the loop body based on the allocated registers.

Abstract: Aspects of the disclosure provide a method for instruction scheduling. The method includes receiving a sequence of instructions, identifying redundant flag-register based dependency of the instructions, and re-ordering the instructions without being restricted by the redundant flag-register based dependency.

Abstract: System and methods are provided for loop process suspension. One or more loop instructions associated with a loop process are loaded in a code cache. One or more branch instructions associated with a branch of the loop process in the code cache are determined. A suspension event is detected. The branch instructions are replaced with one or more jump instructions in the code cache upon the detection of the suspension event. If the jump instructions are executed in the code cache, the branch instructions in the code cache are restored, and the loop process is suspended. One or more suspension instructions associated with the suspension event are executed in an interpreter.

Abstract: Aspects of the disclosure provide a method to support performance analysis. The method includes compiling bytecodes to generate native codes corresponding to the bytecodes in an electronic device, generating a file to include the bytecodes and the corresponding native codes in the file, collecting symbol information to map symbols in the bytecodes with offsets of corresponding native codes, and including the symbol information in the file to enable profiling.

Abstract: System and methods are provided for loop process suspension. One or more loop instructions associated with a loop process are loaded in a code cache. One or more branch instructions associated with a branch of the loop process in the code cache are determined. A suspension event is detected. The branch instructions are replaced with one or more jump instructions in the code cache upon the detection of the suspension event. If the jump instructions are executed in the code cache, the branch instructions in the code cache are restored, and the loop process is suspended. One or more suspension instructions associated with the suspension event are executed in an interpreter.

Abstract: System and methods are provided for register allocation. An original code block and a target code block associated with a branch of an execution loop are determined. An original allocation of a plurality of physical registers to one or more original variables associated with the original code block is detected. A target allocation of the plurality of physical registers to one or more target variables associated with the target code block is determined. One or more temporary registers are selected from the plurality of physical registers based at least in part on the original allocation and the target allocation. The original allocation is changed to the target allocation using the selected temporary registers. Specifically, one or more instructions are generated to change the original allocation to the target allocation using the selected temporary registers. The instructions are executed using one or more processors.

Abstract: Aspects of the disclosure provide a method for instruction scheduling. The method includes receiving a sequence of instructions, identifying redundant flag-register based dependency of the instructions, and re-ordering the instructions without being restricted by the redundant flag-register based dependency.

Abstract: Aspects of the disclosure provide a method for code compilation. The method includes receiving instructions of a loop code for compiling, allocating one or more registers to variables before compiling the instructions into a loop body for the loop code, and compiling the instructions into the loop body based on the allocated registers.

Abstract: In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache.

Abstract: A method, an apparatus, and a system for creating a conference are provided to implement smooth handover from a two-party service to a three-party service in a reserved conference. A method, an apparatus, and a system for operating a conference are disclosed to implement overall operations for an Ad hoc conference. The method for creating a conference includes: an MP creates a conference context according to a received instruction, and adds a conference control termination on the conference context; and the MP applies for conference resources according to a received instruction of modifying attributes of the conference control termination, and modifies current attributes of the conference control termination to create the conference.

Abstract: In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache.

Abstract: In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache.

Abstract: In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache.