Patents by Inventor Liqi Wu

Liqi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12291779
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing the substrate surfaces to a blocking compound to selectively form a blocking layer on at least a portion of the first surface over the second surface. The substrate is sequentially exposed to a metal precursor with a kinetic diameter in excess of 21 angstroms and a reactant to selectively form a metal-containing layer on the second surface over the blocking layer or the first surface. The relatively larger metal precursors of some embodiments allow for the use of blocking layers with gaps or voids without the loss of selectivity.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: May 6, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Bhaskar Jyoti Bhuyan, Mark Saly, David Thompson, Tobin Kaufman-Osborn, Kurt Fredrickson, Thomas Knisley, Liqi Wu
  • Publication number: 20250125195
    Abstract: Embodiments of the disclosure relate to methods using an oligomer film to protect a substrate surface. The oligomer film is formed on the substrate surface with a first feature and a second feature each having a feature depth. The first feature has a first critical dimension (CD) and the second feature has a second CD. The semiconductor substrate surface is exposed to one or more monomers to form the oligomer film, and the oligomer film forms selectively on the bottom and fills a portion of the feature depth. The oligomer film fills the feature depth to substantially the same or the same height in each of the first feature and the second feature. Methods of forming semiconductor devices using the oligomer film are also disclosed.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Xinke Wang, Liqi Wu, Qihao Zhu, Mark Saly, Jiang Lu, John Sudijono, David Thompson
  • Patent number: 12272551
    Abstract: Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 8, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Liqi Wu, Feng Q. Liu, Bhaskar Jyoti Bhuyan, James Hugh Connolly, Zhimin Qi, Jie Zhang, Wei Dou, Aixi Zhang, Mark Saly, Jiang Lu, Rongjun Wang, David Thompson, Xianmin Tang
  • Publication number: 20250112091
    Abstract: A contact structure includes a cavity comprising a device contact formed on a surface of a substrate, a bottom surface, and sidewalls. A metal silicide layer disposed over the surface of the device contact, the bottom surface, and the sidewalls of the cavity, and a treated surface formed over a portion of the metal silicide layer disposed over the sidewalls of the cavity.
    Type: Application
    Filed: September 27, 2024
    Publication date: April 3, 2025
    Inventors: Jianqiu GUO, Dong WANG, Liqi WU, Yiyang WAN, Shumao ZHANG, Qihao ZHU, Weifeng YE, Jiang LU, Shihchung CHEN
  • Publication number: 20250079239
    Abstract: Embodiments of the disclosure include a method of forming a gate-all-around (GAA) contact structure on a semiconductor substrate. The method will include removing material from surfaces of a feature formed in a surface of a substrate that includes a plurality of features that each include a plurality of source/drain contact surfaces, selectively forming a reaction product material over a surface of each of the plurality of source/drain contact surfaces, heating the substrate to a first temperature to remove the reaction product material from the surface of each of the plurality of contacts, selectively forming a first metal layer on the surface of each of the plurality of contacts, selectively forming a second metal layer on the first metal layer, and filling the feature with a conductor material, wherein the conductor material comprises tungsten (W) or molybdenum (Mo).
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Inventors: Jiang LU, Shumao ZHANG, Liqi WU, Yiyang WAN, Weifeng YE, Jianqiu GUO, Dong WANG, Qihao ZHU
  • Publication number: 20250054767
    Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.
    Type: Application
    Filed: April 25, 2024
    Publication date: February 13, 2025
    Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
  • Publication number: 20250054812
    Abstract: Embodiments include a method of forming a contact structure on a semiconductor substrate. The method including selectively depositing a metal silicide layer over a contact formed within a cavity of a substrate and a bottom surface of the cavity using a selective deposition process, including forming a residual layer on a surface of a dielectric layer forming sidewalls of the cavity, wherein a thickness of the metal silicide layer deposited over the contact is greater than a thickness of the residual layer, removing at least a portion of the residual layer formed on the dielectric layer using an etching process that comprises exposing the metal selectively deposited layer to a metal halide containing precursor, and selectively depositing a metal fill over the metal silicide layer remaining over the contact after removing the at least the portion of the residual layer using a selective metal fill process.
    Type: Application
    Filed: December 29, 2023
    Publication date: February 13, 2025
    Inventors: Qihao ZHU, Shumao ZHANG, Weifeng YE, Yiyang WAN, Gary HOW, Jianqiu GUO, Dong WANG, Shihchung CHEN, Liqi WU, Jiang LU
  • Publication number: 20250006555
    Abstract: Embodiments of the disclosure relate to methods of selectively depositing a metal after use of a flowable polymer to protect a substrate surface within a feature. A first metal layer is deposited by physical vapor deposition (PVD). The semiconductor substrate surface is exposed to one or more monomers to form a flowable and flexible polymer film on the first metal layer within the at least one feature. The flowable polymer film forms on the first metal layer on the bottom. The one or more monomers are selected from one or more of amines with bi-functional groups, aldehydes with bi-functional groups, cyanates with bi-functional groups, ketones with bi-functional groups, and alcohols with bi-functional groups. At least a portion of the first metal layer is selectively removed from the top surface and the at least one sidewall. The flowable polymer film is removed.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Feng Q. Liu, Xinke Wang, Liqi Wu, Qihao Zhu, Bhaskar Jyoti Bhuyan, Mark Saly, David Thampson
  • Publication number: 20250006552
    Abstract: Embodiments of the disclosure relate to methods of selectively depositing a metallic material after forming a flowable polymer film to protect a substrate surface within a feature. A first metal liner is deposited by physical vapor deposition (PVD). The flowable polymer film is formed on the first metal liner on the bottom. A portion of the first metal liner is selectively removed from the top surface and the at least one sidewall. The flowable polymer film is removed. In some embodiments, the cycle of depositing a metal liner, forming a flowable polymer film, removing a portion of the metal liner, and removing the flowable polymer film is repeated at least once. A metal layer is deposited on the plurality of metal liners (e.g., first metal liner and the second metal liner) and the metal layer is free of seams or voids.
    Type: Application
    Filed: June 25, 2024
    Publication date: January 2, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Liqi Wu, Rongjun Wang, Feng Q. Liu, Qihao Zhu, Jiang Lu, David Thompson, Xianmin Tang
  • Publication number: 20240404888
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.
    Type: Application
    Filed: August 7, 2024
    Publication date: December 5, 2024
    Applicant: Applied Materuals, Inc.
    Inventors: Thomas Anthony Empante, Avgerinos V. Gelatos, Zhibo Yuan, Liqi Wu, Joung Joo Lee, Byunghoon Yoon
  • Publication number: 20240379363
    Abstract: Methods are provided. In some embodiments, a method of forming a contact structure on a semiconductor substrate includes disposing a selective metal silicide layer on a surface of a contact structure by maintaining a first temperature of a substrate and providing a first carrier gas, a first metal-containing precursor, and a first hydrogen-containing precursor to a first deposition chamber. The method includes disposing a partially selective metal layer on a surface of the selective metal silicide layer and one or more surfaces of a cavity by maintaining a second temperature of the substrate and providing a second carrier gas, a second metal-containing precursor, and a reducing agent to the first deposition chamber or a second deposition chamber. The second metal-containing precursor and the reducing agent are introduced to the first deposition chamber or the second deposition chamber at a chamber pressure of about 50 T to about 150 T.
    Type: Application
    Filed: February 21, 2024
    Publication date: November 14, 2024
    Inventors: Jianqiu GUO, Dong WANG, Shumao ZHANG, Liqi WU, ShihChung CHEN, Jiang LU
  • Publication number: 20240379768
    Abstract: Embodiments of the disclosure include a method of forming contact structure on a semiconductor substrate. The method includes treating a native oxide layer formed on a contact junction, wherein treating the native oxide layer forms a silica salt layer on the contact junction disposed within a contact feature that includes one or more surfaces that comprise silicon nitride. Then exposing the silica salt layer and the one or more surfaces to a plasma comprising oxygen, wherein the plasma forms a silicon oxynitride material on the one or more surfaces. Then removing the second silica salt layer, selectively forming a metal silicide layer on the contact junction, and then filling the contact feature with a metal, wherein filling the feature comprises selectively depositing a metal layer over the selectively formed metal silicide layer.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 14, 2024
    Inventors: Shumao ZHANG, Le ZHANG, Weifeng YE, Chih-Hsun HSU, David T. OR, Gary HOW, Yiyang WAN, Liqi WU, Jiang LU
  • Publication number: 20240371654
    Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Inventors: Qihao ZHU, Chi Hong CHING, Liqi WU, Tsungjui LIU, Gaurav THAREJA, Xinke WANG, Feng Q. LIU, Xi CEN, Kai WU, Yixiong YANG, Yuanhung LIU, Jiang LU, Rongjun WANG, Xianmin TANG
  • Publication number: 20240363407
    Abstract: Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive layer are formed at a temperature of less than 50° C. The method further includes annealing at least a portion of the first conductive layer and the second conductive layer.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Jie ZHANG, Liqi WU, Cory LAFOLLETT, Tsung-Han YANG, Wei WENG, Qihao ZHU, Jiang LU, Rongjun WANG, Xianmin TANG
  • Publication number: 20240352577
    Abstract: Methods and apparatus for selectively depositing a layer atop a substrate having a metal surface and a dielectric surface is disclosed, including: (a) contacting the metal surface with one or more metal halides such as metal chlorides or metal fluorides to form an exposed metal surface; (b) growing an organosilane based self-assembled monolayer atop the dielectric surface; and (c) selectively depositing a layer atop the exposed metal surface of the substrate, wherein the organosilane based self-assembled monolayer inhibits deposition of the layer atop the dielectric surface.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Chang KE, Wenyu ZHANG, Liqi WU
  • Patent number: 12094785
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate may be pre-cleaned. A ruthenium silicide (RuSi) layer is selectively deposited on the p transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. An optional barrier layer may be formed on the titanium silicide (TiSi) layer. The method may be performed in a processing chamber without breaking vacuum.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: September 17, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Thomas Anthony Empante, Avgerinos V. Gelatos, Zhibo Yuan, Liqi Wu, Joung Joo Lee, Byunghoon Yoon
  • Patent number: 12024770
    Abstract: Methods and apparatus for selectively depositing a layer atop a substrate having a metal surface and a dielectric surface is disclosed, including: (a) contacting the metal surface with one or more metal halides such as metal chlorides or metal fluorides to form an exposed metal surface; (b) growing an organosilane based self-assembled monolayer atop the dielectric surface; and (c) selectively depositing a layer atop the exposed metal surface of the substrate, wherein the organosilane based self-assembled monolayer inhibits deposition of the layer atop the dielectric surface.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: July 2, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chang Ke, Wenyu Zhang, Liqi Wu
  • Publication number: 20240105444
    Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.
    Type: Application
    Filed: April 26, 2023
    Publication date: March 28, 2024
    Inventors: Jiang LU, Liqi WU, Wei DOU, Weifeng YE, Shih Chung CHEN, Rongjun WANG, Xianmin TANG, Yiyang WAN, Shumao ZHANG, Jianqiu GUO
  • Publication number: 20240052487
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing the substrate surfaces to a blocking compound to selectively form a blocking layer on at least a portion of the first surface over the second surface. The substrate is sequentially exposed to a metal precursor with a kinetic diameter in excess of 21 angstroms and a reactant to selectively form a metal-containing layer on the second surface over the blocking layer or the first surface. The relatively larger metal precursors of some embodiments allow for the use of blocking layers with gaps or voids without the loss of selectivity.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 15, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Bhaskar Jyoti Bhuyan, Mark Saly, David Thompson, Tobin Kaufman-Osborn, Kurt Fredrickson, Thomas Knisley, Liqi Wu
  • Publication number: 20240038859
    Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.
    Type: Application
    Filed: October 12, 2023
    Publication date: February 1, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Joung Joo Lee, Wenting Hou, Takashi Kuratomi, Avgerinos V. Gelatos, Jianxin Lei, Liqi Wu, Raymond Hoiman Hung, Tae Hong Ha, Xianmin Tang