Patents by Inventor Liqiong Wei

Liqiong Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11024356
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Publication number: 20200020378
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
  • Patent number: 10438640
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Publication number: 20180342277
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 29, 2018
    Applicant: Intel Corporation
    Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
  • Patent number: 10068628
    Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Patent number: 9922691
    Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Pulkit Jain, Fatih Hamzaoglu, Liqiong Wei
  • Patent number: 9875783
    Abstract: Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide thicknesses.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: January 23, 2018
    Assignee: INTEL CORPORATION
    Inventors: Cyrille Dray, Liqiong Wei
  • Patent number: 9865322
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
  • Publication number: 20170169874
    Abstract: Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide thicknesses.
    Type: Application
    Filed: March 3, 2014
    Publication date: June 15, 2017
    Inventors: Cyrille DRAY, Liqiong WEI
  • Publication number: 20170047105
    Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
    Type: Application
    Filed: March 5, 2016
    Publication date: February 16, 2017
    Inventors: PULKIT JAIN, FATIH HAMZAOGLU, LIQIONG WEI
  • Publication number: 20170018298
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
  • Patent number: 9478273
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang
  • Patent number: 9336873
    Abstract: Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Nathaniel J. August, Liqiong Wei
  • Publication number: 20160125927
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Application
    Filed: June 28, 2013
    Publication date: May 5, 2016
    Inventors: Liqiong WEI, Fatih HAMZAOGLU, Yih WANG, Nathaniel J. AUGUST, Blake C. LIN, Cyrille DRAY
  • Patent number: 9286976
    Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: Blake Lin, Cyrille Dray, Ananda Roy, Liqiong Wei, Fatih Hamzaoglu
  • Patent number: 9281043
    Abstract: An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Pulkit Jain, Fatih Hamzaoglu, Liqiong Wei
  • Publication number: 20150348623
    Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Inventors: Blake Lin, Cyrille Dray, Ananda Roy, Liqiong Wei, Faith Hamzaoglu
  • Patent number: 9082509
    Abstract: In some embodiments, detecting resistance in a resistive memory cell may be done using a pulse edge. For example, a pulse may be applied through a resistive memory data cell and another through a reference delay circuit to determine which path has the larger delay in order to determine the resistive state of the data cell in question.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 14, 2015
    Assignee: Intel Corporation
    Inventors: Nathaniel J. August, Liqiong Wei
  • Publication number: 20150155036
    Abstract: Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive memory cell; a detector to generate an output indicating timing relationship between a pulse arriving from the variable resistance memory cell and a pulse arriving from the reference resistive memory cell; and a logic unit to receive the output from the detector and to generate a control signal to the adjust timing relationship as indicated by the detector.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 4, 2015
    Inventors: Nathaniel J. AUGUST, Liqiong WEI
  • Publication number: 20150117095
    Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: Cyrille Dray, Blake C. Lin, Fatih Hamzaoglu, Liqiong Wei, Yih Wang