Patents by Inventor Liran Liss
Liran Liss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11940935Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.Type: GrantFiled: April 19, 2021Date of Patent: March 26, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Eliav Bar-Ilan, Oren Duer, Maxim Gurtovoy, Liran Liss, Aviad Shaul Yehezkel
-
Publication number: 20240095205Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.Type: ApplicationFiled: November 16, 2022Publication date: March 21, 2024Inventors: Daniel Marcovitch, Liran Liss, Aviad Shaul Yehezkel, Rabia Loulou, Oren Duer, Shahaf Shuler, Chenghuan Jia, Philip Browning Johnson, Gal Shalom, Omri Kahalon, Adi Merav Horowitz, Arpit Jain, Eliav Bar-Ilan, Prateek Srivastava
-
Patent number: 11929934Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.Type: GrantFiled: April 27, 2022Date of Patent: March 12, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liran Liss, Ortal Bashan, Aviad Levy, Lion Levi
-
Publication number: 20240072908Abstract: Embodiments are disclosed for facilitating quantum computing over classical and quantum communication channels. An example system includes a network interface card (NIC) apparatus. The NIC apparatus includes an optical receiver, an embedded processor, and a network switch. The optical receiver is configured to receive qubit data via a first communication channel associated with quantum communication. The embedded processor is configured to convert the qubit data into binary bit data. The network switch is configured to output the binary bit data via a second communication channel associated with classical network communication.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Juan Jose Vegas Olmos, Elad Mentovich, Liran Liss, Yonathan Piasetzky
-
Publication number: 20240056411Abstract: System, methods, and devices for providing an address resolution service are provided. In one example, an Address Resolution Service (ARS) node is described as being in communication with one or more endpoints. The ARS node may include one or more circuits that respond to an ARS query message issued by the one or more endpoints with a response message that translates a layer three address to a layer two address.Type: ApplicationFiled: August 9, 2022Publication date: February 15, 2024Inventors: Gal Shalom, Adi Horowitz, Jonatan Piasetzky, Omri Kahalon, Matty Kadosh, Aviad Shaul Yehezkel, Rabia Loulou, Liran Liss
-
Patent number: 11902372Abstract: Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.Type: GrantFiled: May 9, 2023Date of Patent: February 13, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Adi Merav Horowitz, Rabia Loulou, Omri Kahalon, Gal Shalom, Aviad Yehezkel, Asaf Schwartz, Liran Liss
-
Patent number: 11861211Abstract: API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process P1 performed by the first host with access, typically via the bridge chip, to at least local memory buffer M2 residing in the second memory, typically after the access control functionality first validates that process P1 has a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P2, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M2, e.g., via the bridge chip.Type: GrantFiled: December 6, 2021Date of Patent: January 2, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Gal Shalom, Adi Horowitz, Omri Kahalon, Liran Liss, Aviad Yehezkel, Rabie Loulou
-
Patent number: 11848711Abstract: Embodiments are disclosed for facilitating quantum computing over classical and quantum communication channels. An example system includes a network interface card (NIC) apparatus. The NIC apparatus includes an optical receiver, an embedded processor, and a network switch. The optical receiver is configured to receive qubit data via a first communication channel associated with quantum communication. The embedded processor is configured to convert the qubit data into binary bit data. The network switch is configured to output the binary bit data via a second communication channel associated with classical network communication.Type: GrantFiled: February 18, 2022Date of Patent: December 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Juan Jose Vegas Olmos, Elad Mentovich, Liran Liss, Yonathan Piasetzky
-
Patent number: 11836083Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.Type: GrantFiled: November 29, 2021Date of Patent: December 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ran Avraham Koren, Ariel Shahar, Liran Liss, Gabi Liron, Aviad Shaul Yehezkel
-
Publication number: 20230379390Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
-
Publication number: 20230376450Abstract: A method for processing includes receiving a definition of a processing pipeline including multiple sequential processing stages. The processing pipeline is partitioned into a plurality of partitions. The first partition of the processing pipeline is executed on a first computational accelerator, whereby the first computational accelerator writes output data from a final stage of the first partition to an output buffer in a first memory. The output data are copied over a packet communication network to an input buffer in a second memory. The second partition of the processing pipeline is executed on a second computational accelerator using the copied output data in the second memory as input data to a first stage of the second partition.Type: ApplicationFiled: September 14, 2022Publication date: November 23, 2023Inventors: Adit Ranadive, Omri Kahalon, Aviad Shaul Yehezkel, Liran Liss, Gal Shalom, Yorai Itzhak Zack, Tushar Khinvasara
-
Publication number: 20230353499Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Inventors: Liran Liss, Ortal Bashan, Aviad Levy, Lion Levi
-
Publication number: 20230353419Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: ApplicationFiled: July 9, 2023Publication date: November 2, 2023Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
-
Patent number: 11792139Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.Type: GrantFiled: January 24, 2022Date of Patent: October 17, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Boris Pismenny, Ben Ben Ishay, Gal Yefet, Gil Kremer, Avi Urman, Yorai Itzhak Zack, Khalid Manaa, Liran Liss
-
Publication number: 20230315659Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Daniel Marcovitch, Liran Liss, Rabia Loulou, Aviad Yehezkel
-
Publication number: 20230317528Abstract: A metrology system includes metrology equipment, a remote communication link, a local communication link, and a data processing unit (DPU). The metrology equipment is configured to generate a stream of data relating to inspected wafers, and to format the generated data into first and second data types. The remote communication link is configured to communicate with an external system. The data processing unit (DPU) is configured to (i) using the remote communication link, send the data belonging to the first data type directly to the external system, and (ii) perform analysis on the data belonging to the second data type, and, using the local communication link, provide results of the analysis to the metrology equipment.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Juan Jose Vegas Olmos, Oscar Mauricio Forero Camacho, Liran Liss, Elad Mentovich
-
Patent number: 11765079Abstract: A method includes detecting, by an accelerator of a networking device, a serial number of a first data packet is out of order with respect to a previous data packet within a first flow of data packets associated with a packet communication network, wherein the serial number is assigned to the first data packet according to a transport protocol. The method includes reconstructing context data associated with the first flow of data packets, wherein the context data comprises encoding information for encoding of data records containing data conveyed in payloads of data packets in the first flow of data packets according to a storage protocol. The method includes using, by the accelerator, the reconstructed context data in processing a data record associated with a second data packet within the first flow, wherein the second data packet is subsequent to the first data packet in the first flow of data packets.Type: GrantFiled: October 26, 2022Date of Patent: September 19, 2023Assignee: Mellanox Technologies, Ltd.Inventors: Boris Pismenny, Miriam Menes, Idan Burstein, Liran Liss, Noam Bloch, Arie Shahar
-
Patent number: 11765237Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.Type: GrantFiled: April 20, 2022Date of Patent: September 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
-
Patent number: 11757796Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.Type: GrantFiled: September 29, 2021Date of Patent: September 12, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Haggai Eran, Liran Liss, Yuval Shpigelman, Idan Burstein
-
Patent number: 11750418Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: GrantFiled: September 7, 2020Date of Patent: September 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah