Abstract: A method for capturing images on a super-large-scale power equipment (SLSPE) based on a camera free viewing angle is provided, including: determining a first range of the SLSPE and a second range of the camera free viewing angle of each of installed cameras; determining a total number, positions, angles, focal lengths, apertures of the cameras, so as to make, by a synchronous calibration, the combined capturing region fully cover the SLSPE according to the first range and the second range; capturing synchronously images and video and adding timestamps to the captured images and video; performing classified packaging to the captured images and video according to the timestamps, so as to group a plurality of specific images and video captured at the same time into a package; and performing seamlessly splicing on the specific images and video of the package to obtain a seamlessly spliced overall view of the SLSPE.

Abstract: A method for synchronized and distributed processing multi-channel image and video stream based on 5G environment is provided, including: transmitting multi-channel the same pulse signals to a data collecting circuit by a pulse transmitter, the data collecting circuit transmits the pulse signal to an image capturing circuit, and the image capturing circuit triggers a camera capturing system to start to simultaneously capture images and video stream. Distributing multi-channel traffic of the cameras via distributed edge computing and distribution processing, so as to locally process the captured images and video stream directly. Such that, the bandwidth pressure is significantly reduced and the risk of terminal sensitive data information privacy leakage is reduced, too.

Abstract: A computer-implemented method for predicting coal quality of coal mill based on neural network is provided. The method includes: establishing a prediction model based on a neural network structure; importing cleaned coal mill data for model training; connecting the trained prediction model with a distributed control system (DCS) in real time; calculate online the running coal type of the coal mill; and determining the real-time running coal quality of the coal mill according to the calculation results.

Abstract: The present invention discloses a 220 KV transformer sleeve. The sleeve includes a sleeve assembly and a connecting assembly. The sleeve assembly includes a sleeve brace, an adjustable part coupled with the sleeve brace. The connecting assembly includes a rotating part and a mobile part. The sleeve is secured on the transformer core body through screws, and the adjustable part can be opened through the connecting assembly. When maintenance is required, there is no need to dismantle the entire sleeve. The work efficiency is greatly improved. This minimizes inductance leakage and prevents eddy currents from occurring.

Abstract: Provided in the present invention is a 220 KV transformer movable sleeve for easy maintenance which includes a sleeve assembly and a connecting component. The sleeve assembly includes a sleeve and an end cap, and the access port is provided on the sleeve, the access port is matched with the end cap, and the connecting component includes a rotating part, a moving part and a driving part. The access port is arranged on the sleeve assembly, and the inspection can only be carried out by opening the access port during inspection, without dismantling the entire movable sleeve, and greatly improving the work efficiency. The rubber strip is combined with the metal sleeve. The method reduces the influence of magnetic flux leakage on the metal movable sleeve and prevents it from generating eddy current heating. Through the driving part, the end cap can be automatically opened, saving time and effort.

Abstract: A sampling clock generating circuit and an analog to digital converter (ADC) includes a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the variable resistance circuit, and the other end of the variable resistance circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.

Abstract: A sampling clock generating circuit and an analog to digital converter (ADC) includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the resistance variable circuit, and the other end of the resistance variable circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

Abstract: A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

Abstract: Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

Abstract: A sampling clock generating circuit and an analog to digital converter includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; an output end of the NOT-gate type circuit is connected to one end of the capacitor; the other end of the capacitor is grounded; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the resistance variable circuit; and the other end of the resistance variable circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

Abstract: Present invention discloses an ADC and an analog-to-digital conversion method. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.

Abstract: The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.

Abstract: Provided are a level shifter and a digital to analog converter, which can make a minimum value of an output voltage be greater than 0. In the circuit, sources of a first field effect transistor and a second field effect transistor are connected to a first direct current power supply; a drain of the first field effect transistor and a gate of the second field effect transistor are connected to one terminal of a first capacitor; a connecting end formed after the other terminal of the first capacitor is connected to an input end of a phase inverter is used as a digital signal input end; a gate of the first field effect transistor, a drain of the second field effect transistor, a source of a third field effect transistor, and a source of a fifth field effect transistor are connected to one terminal of a second capacitor.

Abstract: Provided are a level shifter and a digital to analog converter, which can make a minimum value of an output voltage be greater than 0. In the circuit, sources of a first field effect transistor and a second field effect transistor are connected to a first direct current power supply; a drain of the first field effect transistor and a gate of the second field effect transistor are connected to one terminal of a first capacitor; a connecting end formed after the other terminal of the first capacitor is connected to an input end of a phase inverter is used as a digital signal input end; a gate of the first field effect transistor, a drain of the second field effect transistor, a source of a third field effect transistor, and a source of a fifth field effect transistor are connected to one terminal of a second capacitor.

Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.