Abstract: A downlink frame processing system (200) includes a packet switch (608) routing self addressed uplink data (706) from an input port to an output port, a memory (804) coupled to the output port, and a downlink scheduler (802) coupled to the memory (804). The memory (804) includes storage for at least two downlink beam hop locations (302, 304). The downlink scheduler (802) processes from one of a plurality of segments at least one scheduling entry (1312) that includes, for example, a header field (1316) defining at least one of a payload and frame type (1404) for at least one of a payload and frame (1200) to be transmitted, and payload data pointers (1502, 1504, 1506) into the memory (804).

Abstract: A power gating module (200) for a downlink beam frame signal (402) includes a power amplifier (210) for amplifying for transmission frame signals that include at least a first header signal (418), a first payload signal (420), a second header signal (424), and a second payload signal (426). The power gating module (200) further includes a power gating circuit (300) coupled to the power amplifier (210). The power gating circuit (300) includes a power gate input (318) and is responsive to a power gating signal to remove power from at least one of the first header signal (418) and first payload signal (420) in combination, and the second header signal (424) and second payload signal (426) in combination before amplification by the power amplifier (210).

Abstract: A method and apparatus for implementing multicast in a space-based communication system is disclosed. The present invention allows for the use of a buffer in which to store data packets prior to replication in a multicast application. The present apparatus includes a buffer (102), a header memory (103), and an ASIC (101) to store and extract received data packets and replicate them as required. The ASIC (101) includes a switch interface (201), a queue manager (203), a header processor (205), a holding buffer (207), and a arbitration interface (209). The switch interface (201) is connected to the queue manager (203). The queue manager (203) is connected to the buffer (102), the header processor 205, the holding buffer (207), and the arbitration and switch interface (204). The header processor (205) is connected to the header memory (103).

Abstract: The method allocates (302) subclass entries in an ordered list (200) (which may be organized as a table, for example). Each entry (210-214) generally corresponds to one of several predetermined cell subclasses, and the allocation reserves a total number of each subclass entry in the ordered list according to a predetermined amount of bandwidth desired for each cell subclass. The subclasses may be associated with factors such as coding rate, downlink beam area, virtual paths or virtual circuits, quality of service parameters, and the like. The method then examines (304) each subclass entry in the ordered list and selects (306) a cell from a cell memory (which may be a queue) that matches the subclass entry. The matched cell is then transmitted (308). The method may also allocate sets of subclass entries in groups corresponding to a frame size and dynamically update (310) the ordered list during operation of the cell switch.