Abstract: A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory.

Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.

Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.

Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.

Abstract: Embodiments relate to exiting a multithreaded guest virtual machine (VM) that is running in a simulation environment. An aspect includes executing the simulation by a guest entity comprising a plurality of logical threads, wherein each of the plurality of logical threads comprises a respective instruction stream. Another aspect includes detecting an exit event corresponding to completion, by a first thread of the plurality of logical threads, of the instruction stream corresponding to the first thread. Another aspect includes, based on determining that the simulation is executing in a redrive mode: based on determining that the TVM of the guest entity indicates that multiple threads of the plurality of logical threads are valid, nullifying a start interpretive execution (SIE) instruction of a host; setting a bit corresponding to the first thread in the TVM to invalid; executing the nullified SIE instruction; and relaunching the guest entity in the redrive mode.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being emulated. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field or the fetch protection field is not enabled.

Abstract: Embodiments relate to exiting a multithreaded guest virtual machine (VM) that is running in a simulation environment. An aspect includes executing the simulation by a guest entity comprising a plurality of logical threads, wherein each of the plurality of logical threads comprises a respective instruction stream. Another aspect includes detecting an exit event corresponding to completion, by a first thread of the plurality of logical threads, of the instruction stream corresponding to the first thread. Another aspect includes, based on determining that the simulation is executing in a redrive mode: based on determining that the TVM of the guest entity indicates that multiple threads of the plurality of logical threads are valid, nullifying a start interpretive execution (SIE) instruction of a host; setting a bit corresponding to the first thread in the TVM to invalid; executing the nullified SIE instruction; and relaunching the guest entity in the redrive mode.

Abstract: An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced.

Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

Abstract: Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Abstract: Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.