Patents by Inventor Lisa Edge

Lisa Edge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device having multiple dielectric gate stacks and related methods
    Patent number: 9006816
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: April 14, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
  • Memory device having multiple dielectric gate stacks with first and second dielectric layers and related methods
    Patent number: 8860123
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Prasanna Khare, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
  • MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS WITH FIRST AND SECOND DIELECTRIC LAYERS AND RELATED METHODS
    Publication number: 20140291750
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Prasanna KHARE, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris
  • MEMORY DEVICE HAVING MULTIPLE DIELECTRIC GATE STACKS AND RELATED METHODS
    Publication number: 20140291749
    Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 2, 2014
    Inventors: Prasanna KHARE, Stephane Allegret-Maret, Nicolas Loubet, Qing Liu, Hemanth Jagannathan, Lisa Edge, Kangguo Cheng, Bruce Doris