Patents by Inventor Lisa F Edge
Lisa F Edge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10930566Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: GrantFiled: January 2, 2020Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Publication number: 20200144134Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: ApplicationFiled: January 2, 2020Publication date: May 7, 2020Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Patent number: 10573565Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: GrantFiled: February 12, 2019Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Publication number: 20190189524Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: ApplicationFiled: February 12, 2019Publication date: June 20, 2019Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Patent number: 10312259Abstract: Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.Type: GrantFiled: July 27, 2016Date of Patent: June 4, 2019Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Lisa F. Edge, Pouya Hashemi, Alexander Reznicek
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Patent number: 10304746Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: GrantFiled: October 11, 2016Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Patent number: 10139358Abstract: In an embodiment, a method comprises fitting a spectroscopic data of a layer in a layered structure to a dielectric function having a real part and an imaginary part; confirming that the dielectric function is physically possible; based on the dielectric function not being physically possible, repeating the fitting the spectroscopic data, or, based on the dielectric function being physically possible, defining an n degree polynomial to the dielectric function; determining a second derivative and a third derivative of the n degree polynomial; equating the second derivative to a first governing equation and the third derivative to a second governing equation and determining a constant of the first governing equation and the second governing equation; and based on the key governing equations, determining one or more of a band gap, a thickness, and a concentration of the layer.Type: GrantFiled: January 11, 2016Date of Patent: November 27, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.Inventors: Lisa F. Edge, Gangadhara R. Muthinti, Shariq Siddiqui
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Publication number: 20170199139Abstract: In an embodiment, a method comprises fitting a spectroscopic data of a layer in a layered structure to a dielectric function having a real part and an imaginary part; confirming that the dielectric function is physically possible; based on the dielectric function not being physically possible, repeating the fitting the spectroscopic data, or, based on the dielectric function being physically possible, defining an n degree polynomial to the dielectric function; determining a second derivative and a third derivative of the n degree polynomial; equating the second derivative to a first governing equation and the third derivative to a second governing equation and determining a constant of the first governing equation and the second governing equation; and based on the key governing equations, determining one or more of a band gap, a thickness, and a concentration of the layer.Type: ApplicationFiled: January 11, 2016Publication date: July 13, 2017Inventors: Lisa F. Edge, Gangadhara R. Muthinti, Shariq Siddiqui
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Publication number: 20170154825Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: ApplicationFiled: October 11, 2016Publication date: June 1, 2017Inventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Publication number: 20160343806Abstract: Methods for fabricating interface passivation layers in a circuit structure are provided. The method includes forming a silicon-germanium layer over a substrate, removing a native oxide layer from an upper surface of the silicon-germanium layer, and exposing the upper surface of the silicon-germanium layer to an ozone-containing solution, resulting in an interface passivation layer with a higher concentration of germanium-dioxide present than germanium-oxide. The resulting interface passivation layer may be part of a gate structure, in which the channel region of the gate structure includes the silicon-germanium layer and the interface passivation layer between the channel region and the dielectric layer of the gate structure has a high concentration of germanium-dioxide.Type: ApplicationFiled: May 21, 2015Publication date: November 24, 2016Applicants: GLOBALFOUNDRIES INC., LAM RESEARCH CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shariq SIDDIQUI, Jody A. FRONHEISER, Murat Kerem AKARVARDAR, Purushothaman SRINIVASAN, Lisa F. EDGE, Gangadhara Raja MUTHINTI, Georges JACOBI, Randolph KNARR
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Patent number: 9502420Abstract: A method is provided that includes providing a material stack of, from bottom to top, a relaxed and n-type doped silicon germanium alloy layer and a relaxed silicon germanium alloy layer, each layer having a uniform germanium content, on a surface of a relaxed and graded silicon germanium alloy buffer layer that is located within a pFET device region of a semiconductor substrate. Next, the relaxed silicon germanium alloy layer is patterned to provide at least one relaxed silicon germanium alloy fin having the uniform germanium content on the relaxed and n-type doped silicon germanium alloy layer. A strained germanium layer is then formed surrounding the at least one relaxed silicon germanium alloy fin. A portion of the strained germanium layer and the at least one relaxed silicon germanium alloy fin can be used as composited channel material for fabricating a pFinFET device.Type: GrantFiled: December 19, 2015Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Lisa F. Edge, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
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Publication number: 20160336345Abstract: Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: BRUCE B. DORIS, Lisa F. Edge, Pouya Hashemi, Alexander Reznicek
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Patent number: 9490161Abstract: Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.Type: GrantFiled: April 29, 2014Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Lisa F. Edge, Pouya Hashemi, Alexander Reznicek
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Patent number: 9490255Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.Type: GrantFiled: December 1, 2015Date of Patent: November 8, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa F. Edge, Hemanth Jagannathan, Paul C. Jamison, Vamsi K. Paruchuri
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Patent number: 9406679Abstract: A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.Type: GrantFiled: July 26, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lisa F. Edge, Hemanth Jagannathan, Balasubramanian S. Haran
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Publication number: 20150333065Abstract: A substrate is provided, having formed thereon a first region and a second region of a complementary type to the first region. A gate dielectric is deposited over the substrate, and a first full metal gate stack is deposited over the gate dielectric. The first full metal gate stack is removed over the first region to produce a resulting structure. Over the resulting structure, a second full metal gate stack is deposited, in contact with the gate dielectric over the first region. The first and second full metal gate stacks are encapsulated.Type: ApplicationFiled: July 26, 2015Publication date: November 19, 2015Inventors: Lisa F. Edge, Hemanth Jagannathan, Balasubramanian S. Haran
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Publication number: 20150311127Abstract: Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.Type: ApplicationFiled: June 15, 2015Publication date: October 29, 2015Inventors: Hemanth Jagannathan, Takashi Ando, Lisa F. Edge, Sufi Zafar, Changhwan Choi, Paul C. Jamison, Vamsi K. Paruchuri, Vijay Narayanan
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Publication number: 20150311109Abstract: Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: International Business Machines CorporationInventors: Bruce B. Doris, Lisa F. Edge, Pouya Hashemi, Alexander Reznicek
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Publication number: 20150311303Abstract: Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.Type: ApplicationFiled: June 15, 2015Publication date: October 29, 2015Inventors: Hemanth Jagannathan, Takashi Ando, Lisa F. Edge, Sufi Zafar, Changhwan Choi, Paul C. Jamison, Vamsi K. Paruchuri, Vijay Narayanan
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Publication number: 20150279746Abstract: Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.Type: ApplicationFiled: June 15, 2015Publication date: October 1, 2015Inventors: Hemanth Jagannathan, Takashi Ando, Lisa F. Edge, Sufi Zafar, Changhwan Choi, Paul C. Jamison, Vamsi K. Paruchuri, Vijay Narayanan