Abstract: An integrated circuit structure is suitable for use with SRAM memory devices. P-channel load devices are used in a 6-transistor SRAM cell. The P-channel devices are formed as polycrystalline silicon field effect transistors above the N-channel field effect transistors, which are formed in the substrate. In order to avoid formation of a P-N junction, a barrier layer is formed between P-type and N-type source/drain regions. The preferred barrier is a bilayer formed from a conductive material such as silicide over a doped polycrystalline silicon layer.

Abstract: A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices.