Abstract: A dual-threaded bushing and spacer assembly capable of accepting standard adhesive staking and thereby enabling compliance with NASA space flight fastener staking requirements. The assembly comprises a bushing having a head with top and bottom surfaces, inner threads, and outer threads, and a spacer having top and bottom surfaces and arranged to accept the bushing. This is achieved by providing a counterbored countersink in the spacer which provides a countersunk surface within the spacer. The countersunk surface provides a contact surface for the bushing head's bottom surface when the bushing is installed in the spacer. The spacer is further arranged such that the countersunk surface is such that, when the bushing is installed, the bushing's top surface is below the spacer's top surface. When so arranged, adhesive staking can be placed between the bushing's top surface and the spacer's vertical counterbored surface.

Abstract: A hybrid device package comprising a baseplate, a balanced composite structure (BCS) on the baseplate, a first IC on the BCS, and at least one additional IC physically coupled to the first IC. The coefficient of thermal expansion (CTE) for the stack formed from the BCS and the first IC is arranged to be approximately equal to that of the baseplate, thereby reducing the thermal stress to which the at least one additional IC is subjected when cooled to its operating temperature which might otherwise result in physical damage to the IC. The baseplate is preferably an alumina ceramic baseplate. In one embodiment, the first IC is a readout IC (ROIC), the at least one additional IC is a detector array IC which is on the ROIC, and the hybrid device package is a focal plane array (FPA).

Abstract: A dual-threaded bushing and spacer assembly capable of accepting standard adhesive staking and thereby enabling compliance with NASA space flight fastener staking requirements. The assembly comprises a bushing having a head with top and bottom surfaces, inner threads, and outer threads, and a spacer having top and bottom surfaces and arranged to accept the bushing. This is achieved by providing a counterbored countersink in the spacer which provides a countersunk surface within the spacer. The countersunk surface provides a contact surface for the bushing head's bottom surface when the bushing is installed in the spacer. The spacer is further arranged such that the countersunk surface is such that, when the bushing is installed, the bushing's top surface is below the spacer's top surface. When so arranged, adhesive staking can be placed between the bushing's top surface and the spacer's vertical counterbored surface.

Abstract: A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ?10 ?m. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.

Abstract: A tiled array of hybrid assemblies and a method of forming such an array enables the assemblies to be placed close together. Each assembly comprises first and second dies, with the second die mounted on and interconnected with the first die. Each vertical edge of a second die which is to be located adjacent to a vertical edge of another second die in the tiled array is etched such that the etched edge is aligned with a vertical edge of the first die. Indium bumps are deposited on a baseplate where the hybrid assemblies are to be mounted, and the assemblies are mounted onto respective indium bumps using a hybridizing machine, enabling the assemblies to be placed close together, preferably ?10 ?m. The first and second dies may be, for example. a detector and a readout IC, or an array of LEDs and a read-in IC.

Abstract: A method of improving the thermal performance of a hybrid assembly which comprises a first die, a second die, and indium bonds which bond and electrically interconnect the first die to the second die. A heat sink plate on which the hybrid assembly is to be mounted is provided. A plurality of indium bumps are deposited on the plate where the assembly is to be mounted. The bottom side of the hybrid assembly is then pressed onto the indium bumps to affix the assembly to the plate. The heat sink plate constrains the lateral coefficient of thermal expansion (CTE) of the second die such that the CTEs of the first and second dies match more closely than they would if the hybrid assembly was not mounted directly to a heat sink plate using indium bumps. The heat sink plate preferably comprises copper tungsten (CuW) or a diamond-metal composite.

Abstract: A hybrid device package comprising a baseplate, a balanced composite structure (BCS) on the baseplate, a first IC on the BCS, and at least one additional IC physically coupled to the first IC. The coefficient of thermal expansion (CTE) for the stack formed from the B CS and the first IC is arranged to be approximately equal to that of the baseplate, thereby reducing the thermal stress to which the at least one additional IC is subjected when cooled to its operating temperature which might otherwise result in physical damage to the IC. The baseplate is preferably an alumina ceramic baseplate. In one embodiment, the first IC is a readout IC (ROIC), the at least one additional IC is a detector array IC which is on the ROIC, and the hybrid device package is a focal plane array (FPA).

Abstract: Pipelined image data transfer which tessellates and quads the data while transferring. The output data from the transfer can be selectively in quad or linear format. Such tessellating and formatting is performed in-line using alternate buffers for pipelining so that there is effectively no delay for performing the operations. The operations are performed by unique input and output buffer and image storage addressing.

Abstract: Bus master for use in computer system includes logic for determining the number of words remaining to be transferred in a DMA operation to supply signals to permit arbitration to start for the next DMA request, thereby avoiding an idle cycle. A timeout state machine is also included to prevent the bus master state machine from hanging in a state with no exit. Errors can be masked to permit analysis of system problems.