Patents by Inventor Lisa Pallotti

Lisa Pallotti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7814301
    Abstract: In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: October 12, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rangaswamy Arumugham, Mark Shaw, Russ W. Herrell, Lisa Pallotti
  • Patent number: 7809025
    Abstract: There is provided a method of operating a computer system. The computer system comprises at least two cabinets and the at least two cabinets have at least one clock signal. The method includes selecting one of the at least one clock signal to serve as a master signal, and synchronizing the computer system to operate from the master signal. Additionally, the method includes altering the capacity of the system while the system is operating.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 5, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rangaswamy Arumugham, Lisa Pallotti
  • Publication number: 20080256379
    Abstract: In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.
    Type: Application
    Filed: April 11, 2007
    Publication date: October 16, 2008
    Inventors: Rangaswamy Arumugham, Mark Shaw, Russ W. Herrell, Lisa Pallotti
  • Publication number: 20080080566
    Abstract: There is provided a method of operating a computer system. The computer system comprises at least two cabinets and the at least two cabinets have at least one clock signal. The method includes selecting one of the at least one clock signal to serve as a master signal, and synchronizing the computer system to operate from the master signal. Additionally, the method includes altering the capacity of the system while the system is operating.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Rangaswamy Arumugham, Lisa Pallotti
  • Publication number: 20060218348
    Abstract: A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type of device that uses a first cache-line size; and a plurality of second ports, each second port configured to receive communications from a second type of device that uses a second cache-line size, such that communications between the first type of devices are enabled over a plurality of first routes, such that communications between the second type of devices are enabled over a plurality of second routes, and such that communications between the first type of devices and the second type of devices are disabled.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 28, 2006
    Inventors: Mark Shaw, Gary Gostin, Lisa Pallotti