Patents by Inventor Lisa R. Zeimantz

Lisa R. Zeimantz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit defect review and classification process
    Patent number: 6654114
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: November 25, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Publication number: 20020191181
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Application
    Filed: August 5, 2002
    Publication date: December 19, 2002
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Patent number: 6441897
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 27, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Patent number: 6373566
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: April 16, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Publication number: 20020024661
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Application
    Filed: August 28, 2001
    Publication date: February 28, 2002
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Publication number: 20010015803
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprising the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Application
    Filed: April 20, 2001
    Publication date: August 23, 2001
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Patent number: 6259520
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprising the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: July 10, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Lisa R. Zeimantz
  • Integrated circuit defect review and classification process
    Patent number: 6072574
    Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprising the steps of visually inspecting said dice on said wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of said dice on said wafer, and determining if said wafer is acceptable to proceed in said manufacturing process.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: June 6, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Lisa R. Zeimantz