Abstract: A 90-degree, 3 dB coupler has an input port, an isolated port, a first output port, and a second output port. A plurality of solenoid structures are arranged in a parallel, spaced relationship. A first group of the interconnects bridge the solenoid structures of a first set that define a first contiguous connection from the input port to the first output port. A second group of interconnects bridge the solenoid structures of a second set that define a second contiguous connection from the isolated port to the second output port. A third group of interconnects bridge the solenoid structures of a third set that define a third contiguous connection from the isolated port to the second output port. The solenoid structures are each unique to a respective one of the first set, second set, and the third set.

Abstract: A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

Abstract: A 90-degree 3 dB coupler with an input port, an isolated port, a first output port, and a second output port has an input connector strip connected to the input port, and an isolated port connector strip connected to the isolated port. A first output connector strip is connected to the first output port, and a second output connector strip is connected to the second output port. A first interconnect strip is connected to the input connector strip and a second interconnect strip is connected to the isolated port connector strip. A first one of conductive coupled strips extend from the input connector strip to the second output connector strip, while a second one of the conductive coupled strips extend from the first interconnect strip to the second interconnect strip. A third one of the conductive coupled strips extends from the first interconnect strip to the second output connector strip.

Abstract: A resonant switch with a first port and a second port has a capacitor connected thereto. A triple inductor network has a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled thereto. In a deactivated state, the center inductor and the capacitor define a parallel resonance at a predefined operating frequency range, and in an activated state, insertion loss associated with the center inductor is substantially minimized to metallic trace loss attributable thereto.

Abstract: An ultra-high coupling factor transformer has a plurality of conductive layers, a primary winding inductor, and a secondary winding inductor. The primary winding inductor is defined by a plurality of turns and disposed on a first one of the plurality of conductive layers and extends to a second one of the plurality of conductive layers. The secondary winding inductor is defined by a plurality of turns and disposed on the first one of the plurality of conductive layers and extends to the second one of the plurality of conductive layers. The primary winding is vertically and horizontally cross coupled with the secondary winding inductor, and defines a mutual coupling inductance from surrounding directions.

Abstract: A phase shifter with a first port and a second port has a triple inductor network with a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled to the center inductor. A resistance switch network that is connected to the first and second peripheral inductors. The resistance switch network is selectively activatable to set a first state defined at least by a first resistance in a series circuit with the first and second peripheral inductors, a second state defined at least by a second resistance in the series circuit, and a third state defined at least by a third resistance in the series circuit. A transmission signal from the first port to the second port is shifted in phase by a prescribed angle corresponding to forward transmission coefficients for the first state, second state, and third state.

Abstract: An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

Abstract: A power splitter-combiner with a combined port and a plurality of split ports has a first coupled inductor pair with each inductor connected to the combined port. A second coupled inductor pair is connected to one of the inductors of the first coupled inductor pair. A first inductor of the second coupled inductor pair is connected to a first split port, and a second one of the second coupled inductor pair is connected to a second split port. A third coupled inductor pair is connected to a second one of the inductors of the first coupled inductor pair. A first one of the inductors of the third coupled inductor pair is connected to a third split port, and a second one of the inductors of the third coupled inductor pair is connected to a fourth split port.

Abstract: A phase shifter with a first port and a second port has a triple inductor network with a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled to the center inductor. A resistance switch network that is connected to the first and second peripheral inductors. The resistance switch network is selectively activatable to set a first state defined at least by a first resistance in a series circuit with the first and second peripheral inductors, a second state defined at least by a second resistance in the series circuit, and a third state defined at least by a third resistance in the series circuit. A transmission signal from the first port to the second port is shifted in phase by a prescribed angle corresponding to forward transmission coefficients for the first state, second state, and third state.

Abstract: A resonant switch with a first port and a second port has a capacitor connected thereto. A triple inductor network has a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled thereto. In a deactivated state, the center inductor and the capacitor define a parallel resonance at a predefined operating frequency range, and in an activated state, insertion loss associated with the center inductor is substantially minimized to metallic trace loss attributable thereto.

Abstract: A cooling structure for a silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) includes a plurality of semiconductor strips separated from each other by isolation trenches, each of the semiconductor strips extending away from a transistor P-well disposed on top of a buried oxide (BOX) layer formed in a semiconductor substrate and having first and second ends, the second end being farther than the first end from the transistor P-well. Applying a voltage to the plurality of semiconductor strips may generate, in at least one of the strips, a first area having a reduced temperature closer to the first end than to the second end of the strip and a second area having an increased temperature closer to the second end than to the first end of the strip. The first and second areas may be generated by the Peltier effect.

Abstract: A semiconductor die and a transmission line structure has a first doped semiconductor substrate and a radio frequency transmission line disposed above the first doped semiconductor substrate. A second doped semiconductor segment is defined in the first doped semiconductor substrate and is arranged in a transverse relationship to a transmission line axis, with a depletion region being defined in areas of the first doped semiconductor substrate adjacent thereto that reduces power loss in signals through the transmission line.

Abstract: A phased array beamformer circuit connectible to an array of antenna elements has RF input/output ports, and splitter-combiners with a combined port and one or more split ports. Transmit/receive circuits are connected to the split ports and to the antenna elements of the array. The transmit/receive circuits have transmit chain and a receive chain, with power sense circuits connected thereto that output reception power level signals corresponding to detected power levels of signals through the receive chain. Gain controllers connected to each of the receive chains and to the power sense circuits adjust the gain of the receive chains based upon control signals outputted thereby.

Abstract: A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

Abstract: A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

Abstract: A zero insertion loss directional coupler includes an input port, an antenna port, an isolation port, and a detect port. The coupler has a first signal trace, a second signal trace, and an inductive winding. The first signal trace is on one of two layers and is connected to the input port and the antenna port, while the inductive winding is on another one of the two layers. A first terminal of the inductive winding is connected to the isolation port. A first terminal of the second signal trace is connected to the detect port and a second terminal of the second signal trace is connected to a second terminal of the inductive winding.

Abstract: An RF power limiter and ESD protection circuit has a set of two CMOS FETs each configured to perform a diode function with a defined forward voltage and arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal. When an RF signal is applied symmetrically to the input terminal and ground terminal it becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured CMOS FETs. In the ESD protection mode one of the CMOS FETs acts as a grounded gate NMOS transistor with SCR action to provide for mitigation of voltage and current over-stress of transistors utilized in RF transceiver circuits. Generally, the circuit architectures allow input power levels to be limited to an extent that reliable operation can be maintained.

Abstract: An RF receiver circuit configuration and design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection. The invention provides combined circuits of an RF transceiver architecture that measure antenna reflected power relative to forward power using the error amplifier signal to adjust the gain of the variable gain amplifier in order to compensate for the mismatch between forward reflected power and forward power at the antenna in order to achieve constant radiated power. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

Abstract: A radio frequency (RF) power amplifier circuit with a diode linearizer circuit. The power amplifier circuit has an input and an output, as well as a power amplifier transistor with a first terminal connected to the input, a second terminal connected to the output, and a third terminal. The linearizer circuit is connected to the third terminal and to ground, and has a non-linear current-voltage curve as well as a non-linear capacitance. The linearizer circuit reduces inter-modulation products in a current through the power amplifier transistor from the second terminal to the third terminal that corresponds to an input signal applied to the input.

Abstract: An RF receiver circuit configuration and design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection. The invention provides combined circuits of an RF transceiver architecture that measure antenna reflected power relative to forward power using the error amplifier signal to adjust the gain of the variable gain amplifier in order to compensate for the mismatch between forward reflected power and forward power at the antenna in order to achieve constant radiated power. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.