Abstract: A display panel and a display apparatus are provided. The display panel includes a display layer, a package layer, and a functional film layer that are stacked in sequence, where the display layer includes a plurality of light emitting devices. The functional film layer is located on a side of the package layer that is far away from the display layer, the functional film layer includes at least one elastic recovery layer, and the display panel includes a bendable area. The elastic recovery layer is at least located in the bendable area. The elastic recovery layer can assist another film layer in performing arching recovery after bending, thereby reducing a risk that repeated bending causes film layer stripping or rupture and the arching of the bending part cannot be recovered in the flattened state.

Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.

Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.

Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.

Abstract: The present invention teaches a TFT substrate manufacturing method and a TFT substrate. The method configures contact region vias in the source/drain contact regions at two ends of the active layer, provides buffer layer troughs in the buffer layer beneath the contact region vias, and forms undercut structure between the buffer layer troughs and the active layer around the contact region vias, thereby separating the transparent conductive layer at the contact region vias, and extending the source/drain electrodes to contact the source/drain contact regions of the active layer from below through the buffer layer troughs. The present invention therefore prevents the occurrence of Schottky contact barrier resulted from the contact between poly-Si and ITO in the 7-mask process by letting the source/drain electrodes to directly contact and form ohmic contact with the source/drain contact regions of the active layer, thereby enhancing the electronic mobility of TFT devices.

Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.

Abstract: The present invention teaches a LTPS TFT substrate and its manufacturing method. The manufacturing method, after forming vias using the photoresist layer on the ILD layer and the gate insulation layer above the source/drain contact regions, and before peeling the photoresist layer, forms conductive layers in the vias by depositing conductive material in the vias. The source/drain electrodes contact the conductive layers in the vias and therefore are conducted to the source/drain contact regions, thereby effectively resolving the problem of contact impedance being too high between the source/drain electrodes and the source/drain contact regions from the existing re-etch LDD technique. Then, through the re-etch LDD technique, the present invention is able to omit a mask process without sacrificing product characteristics.

Abstract: The CMOS LTPS TFT substrate manufacturing method, by a semi-transparent mask, forms a second photoresist pattern having a second photoresist section above a second poly-Si active layer where P-type ion heavy doping is to be performed as protection. Then, N-type ions are effectively prevented from being implanted into the second poly-Si active layer's second source/drain contact region when conducting N-type ion heaving doping to the first poly-Si active layer. There is no need to compensate P-type ions during the subsequent P-type ion heavy doping to the second poly-Si active layer for forming the second source/drain contact region. The present invention therefore reduces the productivity loss in the P-type ion heaving doping process and, as N-type ion heaving doping does not affect the PMOS transistors, enhances the electrical convergence of the PMOS transistors. Damage to the film lattice structure by the ion implantation is also reduced, thereby increasing the device reliability.

Abstract: A type of LED lamp structure and its preparation process are disclosed, where insulation casings are placed over two thin wires extended from the bulb shell to prevent the two electrodes from contacting before they are electrically connected with the driver power supply, usually by welding or winding. The LED lamp structure of the embodiments of the present invention includes: light-emitting components, driver power supply and electrical connection components; the light-emitting components include an LED lamp pole. Thick wires are installed below the LED lamp pole and the thick wires are electrically connected to the LED lamp pole; the driver power supply includes the driver circuit board and the driver circuit board is connected to the female connector for plugging to the thick wires, so that the thick wires are electrically connected to the driver power supply through the female connector.

Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less or equal to 35 nm.

Abstract: A type of LED lamp structure and its preparation process are disclosed, where insulation casings are placed over two thin wires extended from the bulb shell to prevent the two electrodes from contacting before they are electrically connected with the driver power supply, usually by welding or winding. The LED lamp structure of the embodiments of the present invention includes: light-emitting components, driver power supply and electrical connection components; the light-emitting components include an LED lamp pole. Thick wires are installed below the LED lamp pole and the thick wires are electrically connected to the LED lamp pole; the driver power supply includes the driver circuit board and the driver circuit board is connected to the female connector for plugging to the thick wires, so that the thick wires are electrically connected to the driver power supply through the female connector.

Abstract: The present invention teaches a LTPS TFT substrate and its manufacturing method. The manufacturing method, after forming vias using the photoresist layer on the ILD layer and the gate insulation layer above the source/drain contact regions, and before peeling the photoresist layer, forms conductive layers in the vias by depositing conductive material in the vias. The source/drain electrodes contact the conductive layers in the vias and therefore are conducted to the source/drain contact regions, thereby effectively resolving the problem of contact impedance being too high between the source/drain electrodes and the source/drain contact regions from the existing re-etch LDD technique. Then, through the re-etch LDD technique, the present invention is able to omit a mask process without sacrificing product characteristics.

Abstract: Described are a method and apparatus for the biological treatment of wastewater in an activated sludge process that use a primary separator to produce a pretreated wastewater, a pressurized aeration tank which has a headspace pressure of between about 1 and about 10 psi, and a secondary separator to separate mixed liquor from the aeration tank into an activated sludge component and a clarified liquor component. The aeration tank has a rectangular or square base and may be cuboid. Embodiments contemplate making a package plant, and may use a screening tank, a membrane separator, air eductors to aerate a return activated sludge, and multiplier nozzles to introduce the return activated sludge into the aeration tank. The apparatus has a small footprint, is simple in design, and is low maintenance.

Abstract: The present invention provides a fluidized catalytic process for production of dimethyl ether from methanol, wherein said process is carried out in a reactor in which the catalyst is in a fluidized state. Said process comprises the following steps of (1) feeding the methanol feedstock via two or more locations selected from the bottom, lower part, middle part and upper part of the reactor, contacting with the catalyst for preparation of dimethyl ether by methanol dehydration, carrying out the reaction of preparing dimethyl ether by methanol dehydration to obtain the reaction stream, separating said reaction stream to obtain a coked catalyst and a crude product primarily containing the target product, i.e. dimethyl ether; (2) totally or partially feeding the coked catalyst obtained in step (1) into a regenerator in a continuous or batch manner for regeneration via coke-burning, the regenerated catalyst being directly recycled to step (1) after being totally or partially cooled.

Abstract: The present invention provides a fluidized catalytic process for production of dimethyl ether from methanol, wherein said process is carried out in a reactor in which the catalyst is in a fluidized state. Said process comprises the following steps of (1) feeding the methanol feedstock via two or more locations selected from the bottom, lower part, middle part and upper part of the reactor, contacting with the catalyst for preparation of dimethyl ether by methanol dehydration, carrying out the reaction of preparing dimethyl ether by methanol dehydration to obtain the reaction stream, separating said reaction stream to obtain a coked catalyst and a crude product primarily containing the target product, i.e. dimethyl ether; (2) totally or partially feeding the coked catalyst obtained in step (1) into a regenerator in a continuous or batch manner for regeneration via coke-burning, the regenerated catalyst being directly recycled to step (1) after being totally or partially cooled.