Abstract: A method for three-dimensional memory stacking may include providing a logic die including a circuit and a memory, providing a memory die including an additional memory having a same footprint as the circuit and memory in the logic die, and stacking the logic die and the memory die three-dimensionally with die-to-die data communication between the circuit and the additional memory by face-to-face hybrid bonds. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for three-dimensionally stacking systems on chip with face to face hybrid bonding may include providing a first die including a driver gate driving a first via ladder coupled to a first top metal layer. The method may additionally include providing a second die including a load gate coupled to a second via ladder coupled to a second top metal layer. The method may also include stacking the first die and the second die three-dimensionally using face-to-face hybrid bonds to couple the first top metal layer to the second top metal layer. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for non-uniform memory access on three-dimensionally-stacked hybrid memory may include providing a logic die including a circuit and a memory. The method may additionally include providing a plurality of memory dies including an additional memory. The method may also include stacking the logic die and the plurality of memory dies three-dimensionally using face-to-face hybrid bonds that provide non-uniform access to the additional memory by the circuit. Various other methods, systems, and computer-readable media are also disclosed.