Abstract: A rotatable transmission electron microscope (TEM) grid holder includes first and second legs orthogonally positioned with respect to each other. Each clamp holder leg is configured to be received within a hole in a main stage supporting the rotatable TEM grid holder. When the first leg of the clamp holder is affixed within the main stage, the sample has a first orientation with respect to the FIB, and when second leg of the clamp holder is affixed within the main stage, the sample has a second orientation with respect to the FIB, rotated 90° relative to the first orientation. The sample may be rotated back and forth between the first and second orientations multiple times as needed to produce a sample which may be clearly imaged by the TEM system, substantially free of curtaining effects.

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

Abstract: Technology is disclosed herein for early erase termination as a counter-measure for erase disturb. Multiple erase blocks of NAND memory cells are erased in parallel during an erase procedure. Erasing multiple erase blocks in parallel can place considerable strain on the circuitry that generates the erase voltage. If there is significant leakage current in one of the erase blocks the magnitude of the erase voltage for all of the erase blocks may drop. The erase blocks are tested sequentially for leakage current during the first erase loop while the erase voltage is applied to only the erase block under test. If any erase block fails the leakage current test that erase block is removed from the erase procedure. One or more additional erase loops are then performed with only those erase blocks that passed the leakage current test simultaneously receiving an erase voltage, thereby preventing erase disturb with early termination.

Abstract: An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining based on the first count a first drain-to-gate voltage of the first select transistor, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current, and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.

Abstract: An erase process for a group of non-volatile memory cells comprises applying doses of erasing to the group and performing erase verify between pairs of successive doses of erasing. The time needed to complete the erase process can be reduced by optimizing the order of performing erase verify. For example, erase verify can be performed by separately performing erase verify for multiple portions of the group in order from previously determined slowest erasing portion of the group to previously determined fastest erasing portion of the group, and aborting the performing of erase verify prior to completion of erase verify for all of the portions of the group in response to a number erase errors exceeding a limit.

Abstract: An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining a threshold number based on the first count, and determining whether the erase operation passed or failed based on the threshold number.

Abstract: To prevent loss of data due to a word line to memory hole short (or another defect), it is proposed to perform an erase process for a plurality of memory cells, detect that a subset of the plurality of memory cells are slow to erase, and prevent successfully programming for at least some of the memory cells that are slow to erase. This technique uses the erase process to predict future word line to memory hole shorts and prevent programming of memory cells predicted to have a future word line to memory hole short so no data will be lost when the short manifests.

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.

Abstract: A source side programming method and system are provided. A bad trigger block, of a plurality of blocks of a memory array, may be detected by determining a threshold voltage distribution of a drain side select gate of a block and determining whether the distribution is abnormal. If the distribution is abnormal, the block is a bad trigger block which may cause a failure in another block. IF the block is a bad trigger block, source side programming is performed on at least one word line of the bad trigger block by applying a non-zero voltage to at least one source side word line of the bad trigger block via a source side line.