Abstract: The present application discloses a method for preparing a TEM sample, comprising: step 1, step 1, providing a chip sample having a metal protective layer formed on a first surface; step 2, fixing the chip sample on a sample table of a FIB system; step 3, performing the first time of FIB cutting on the metal protective layer along a first direction, so as to form a groove, wherein the first direction is the width direction of the TEM sample, and the inner side surface of the groove is arc-shaped so that the thickness of the metal protective layer in a groove area gradually changes; and step 4, performing the second time of FIB cutting along a third direction to thin the chip sample and form the TEM sample, wherein the third direction is a direction from the metal protective layer to the chip sample.

Abstract: The present invention discloses a universal wheel. A roller is rotationally connected to a mounting base. One side of the roller is provided with an annular channel and limiting grooves. The mounting base is provided with an arc-shaped elastic limiting through hole, a locking position, an unlocking position, and a positioning part. A middle position of a brake lever is pivotally connected to the mounting base, with one end for driving and the other end for a brake rod to pass through and slide and push the positioning part, enabling the brake rod to switch between the locking position and unlocking position. The present invention simplifies an assembly process while implementing effective braking.

Abstract: Provided are a new compound as represented by formula (I) having a dual antagonistic effect of an angiotensin II receptor and an endothelin receptor, and the use thereof in the preparation of a drug.

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Abstract: Disclosed are a ship arrival prediction system and a ship arrival prediction method. The system includes a data acquisition module for acquiring historical sample data of a ship arrival; a data processing module connected with the data acquisition module and used for processing the historical sample data and converting the processed data into a two-dimensional matrix; a spatial temporal graph convolution layer module connected with the data processing module and used for modeling the converted data and obtaining optimal model parameters through training operations; and a full connection module connected with the spatial temporal graph convolution layer module and used for carrying out a dimensional reconstruction on an output result of the spatial temporal graph convolution layer module and outputting to obtain a predictive value of the ship arrival in each port.

Abstract: A room-temperature semiconductor maser, including a first matching network, a second matching network, a heterojunction-containing transistor, and a resonant network. The output end of the first matching network is connected to the drain of the heterojunction-containing transistor. The input end of the second matching network is connected to the source of the heterojunction-containing transistor. The gate of the heterojunction-containing transistor is connected to the resonant network. The pumped microwaves are fed into the input end of the first matching network.

Abstract: A synthesis and screening method of a DNA-encoded compound library. The DNA-encoded compound library consists of a DNA-encoded compound of formula (I). The screening method includes: incubating the DNA-encoded compound library with a protein target, followed by covalent cross-linking to obtain a covalently cross-linked complex; separating the covalently cross-linked complex from members in the library that do not bind to the protein target; and subjecting the covalently cross-linked complex to polymerase chain reaction (PCR) amplification and DNA sequencing.

Abstract: The present application discloses a method for preparing a TEM sample, comprising: step 1, step 1, providing a chip sample having a metal protective layer formed on a first surface; step 2, fixing the chip sample on a sample table of a FIB system; step 3, performing the first time of FIB cutting on the metal protective layer along a first direction, so as to form a groove, wherein the first direction is the width direction of the TEM sample, and the inner side surface of the groove is arc-shaped so that the thickness of the metal protective layer in a groove area gradually changes; and step 4, performing the second time of FIB cutting along a third direction to thin the chip sample and form the TEM sample, wherein the third direction is a direction from the metal protective layer to the chip sample.

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a laminate inlay embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the laminate inlay and configured to distribute a load current switched by the laminate inlay. A fourth metal layer is positioned between the second metal layer and the laminate inlay and configured as a primary thermal conduction path for heat generated by the laminate inlay during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: An apparatus comprising: at least one memory; instructions; and processor circuitry to execute the instructions to: processor circuitry to execute the instructions to: identify a word in an image, the word to be converted to an audio waveform; encode the word identified in the image into an ordered list of phonemes; and synthesize the audio waveform of the word based on an output of a neural network that determines a duration that a phoneme of the ordered list of phonemes is to be expressed in the audio waveform.

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

Abstract: A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.

Abstract: A method and a device for displaying a motion path of robot and a robot. The method for displaying a motion path of the robot includes acquiring a current motion path of the robot, recognizing the motion path to determine a type of the motion path, determining, according to the type of the motion path, a display manner corresponding to the type of the motion path, and displaying the motion path on an electronic map in the determined display manner.

Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.

Abstract: A power electronic assembly includes a board having metal layers laminated onto or between electrically insulating layers, and a power device embedded in the board. A first metal layer provides electrical contacts at a first side of the board. A second metal layer provides a thermal contact at a second side of the board. A third metal layer is positioned between the first metal layer and the power device and configured to distribute a load current switched by the power device. A fourth metal layer is positioned between the second metal layer and the power device and configured as a primary thermal conduction path for heat generated by the power device during switching of the load current. A first electrically insulating layer separates the fourth metal layer from the second metal layer so that the fourth metal layer is electrically isolated from but thermally connected to the second metal layer.

Abstract: A room-temperature semiconductor maser, including a first matching network, a second matching network, a heterojunction-containing transistor, and a resonant network. The output end of the first matching network is connected to the drain of the heterojunction-containing transistor. The input end of the second matching network is connected to the source of the heterojunction-containing transistor. The gate of the heterojunction-containing transistor is connected to the resonant network. The pumped microwaves are fed into the input end of the first matching network.

Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.

Abstract: The present invention relates to the field of reliability-based structural design optimization, and provides an integration method for accurate modeling and analysis and reliability-based design optimization of variable stiffness composite plate and shell structures. In this method, the first-order reliability method, two-point adaptive nonlinear approximation and second-order reliability method are applied into the efficient reliability-based design optimization of variable stiffness composite plate and shell structures. The fiber placement path of variable stiffness composite plate and shell structures is accurately modeled by non-uniform rational B-spline function. Isogeometric analysis is utilized for the variable stiffness composite plate and shell structures, including conducting linear buckling analysis on the variable stiffness composite plate and shell structures based on the isogeometric analysis method and deriving analytical sensitivity of design and random variables on the structural response.