Patents by Inventor Liu Guo Lin

Liu Guo Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7838439
    Abstract: A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: November 23, 2010
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masaharu Oshima, Haruhiko Takahashi, Koji Usuda, Ziyuan Liu, Liu Guo-lin, Kazuto Ikeda, Masaki Yoshimaru
  • Publication number: 20090004886
    Abstract: A stacked film has an insulating film containing hafnium formed above a silicon layer and a polysilicon layer formed on the insulating film. The stacked film is heated in an atmosphere containing oxygen and nitrogen and having the total pressure approximately equal to a partial pressure of the nitrogen.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Masaharu OSHIMA, Haruhiko TAKAHASHI, Koji USUDA, Ziyuan LIU, Liu GUO-LIN, Kazuto IKEDA, Masaki YOSHIMARU
  • Patent number: 6806190
    Abstract: In order to prevent silicides from getting under side walls when the silicides are formed over MOSFET formed over an SOI substrate, trenches are defined in the SOI substrate and side walls are formed over the trenches, whereby the silicides are blocked so as not to get under a gate insulator with a lower portion of each side wall as a structure convex in a downward direction of the substrate. Thus, an increase in gate withstand voltage, a decrease in gate leakage current and control on a short channel effect are achieved.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: October 19, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Liu Guo Lin
  • Patent number: 6782072
    Abstract: A method of analyzing a composition depth profile of a solid surface layer, wherein actually-measured intensity of photoelectrons emitted from the solid surface layer by irradiating the solid surface layer containing at least two or more species of element with X rays and photoelectron calculated intensity obtained by making a calculation assuming an elemental composition ratio for each of a plurality of sub-layers into which the solid surface layer has been temporarily divided are utilized to determine a composition depth profile of the solid surface layer, the method including a step of at least repeating an approximate calculation including: distinguishing a specified sub-layer such that the calculated intensity best converges to the actually-measured intensity in the sub-layers; and correcting an elemental composition ratio at least for the specified sub-layer so that the calculated intensity converges to the actually-measured intensity, thereby determining the composition depth profile of the solid surfa
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: August 24, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Liu guo Lin
  • Publication number: 20040071270
    Abstract: A method of analyzing a composition depth profile of a solid surface layer, wherein actually-measured intensity of photoelectrons emitted from the solid surface layer by irradiating the solid surface layer containing at least two or more species of element with X rays and photoelectron calculated intensity obtained by making a calculation assuming an elemental composition ratio for each of a plurality of sub-layers into which the solid surface layer has been temporarily divided are utilized to determine a composition depth profile of the solid surface layer, the method including a step of at least repeating an approximate calculation including: distinguishing a specified sub-layer such that the calculated intensity best converges to the actually-measured intensity in the sub-layers; and correcting an elemental composition ratio at least for the specified sub-layer so that the calculated intensity converges to the actually-measured intensity, thereby determining the composition depth profile of the solid surfa
    Type: Application
    Filed: April 24, 2003
    Publication date: April 15, 2004
    Inventor: Liu guo Lin
  • Publication number: 20030155620
    Abstract: In order to prevent suicides from getting under side walls when the suicides are formed over MOSFET formed over an SOT substrate, trenches are defined in the SOI substrate and side walls are formed over the trenches, whereby the suicides are blocked so as not to get under a gate insulator with a lower portion of each side wall as a structure convex in a downward direction of the substrate. Thus, an increase in gate withstand voltage, a decrease in gate leakage current and control on a short channel effect are achieved.
    Type: Application
    Filed: December 21, 2001
    Publication date: August 21, 2003
    Inventor: Liu Guo Lin
  • Patent number: 6225137
    Abstract: The semiconductor wafer evaluation method of the present invention comprises the steps of: preparing a substrate embedded with an oxide film; removing the oxide film from a surface of the substrate so as to expose a silicon layer; removing silicon portions within the silicon film and the embedded oxide film by etching so as to form holes within the embedded oxide layer in a first etching step; removing the silicon substrate below the holes by etching in a second etching step; and measuring and evaluating the holes enlarged by the first and second etching steps.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: May 1, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Liu Guo Lin