Patents by Inventor Liu HAN

Liu HAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288786
    Abstract: A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: April 29, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: Yang Zhou, Liu Han, Qingchao Meng, XinYong Wang, ZeJian Cai
  • Publication number: 20250096783
    Abstract: A scan flip-flop circuit includes first and second I/O nodes, a flip-flop circuit, a selection circuit configured to receive a scan direction signal and including input terminals coupled to the first and second I/O nodes and an output terminal coupled to an input terminal of the flip-flop circuit, and first and second drivers configured to receive the scan direction signal and a scan enable signal, each including an input terminal coupled to an output terminal of the flip-flop circuit and an output terminal coupled to a respective first or second input terminal of the selection circuit. Responsive to the scan direction and scan enable signals, one of the first driver is configured to output a first signal responsive to a second signal received at the second input terminal or the second driver is configured to output a third signal responsive to a fourth signal received at the first input terminal.
    Type: Application
    Filed: December 4, 2024
    Publication date: March 20, 2025
    Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
  • Publication number: 20250072117
    Abstract: An IC structure includes first through third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by corresponding spaces, a first plurality of active areas, gate structures, and metal-like defined (MD) segments overlying and electrically connected to the active areas positioned in the first n-well, a first tap structure overlying and electrically connected to the second n-well, a second tap structure overlying and electrically connected to the third n-well, and a first metal segment extending in the first direction, overlying the first plurality of transistors, and electrically connected to each of the first and second tap structures.
    Type: Application
    Filed: September 18, 2023
    Publication date: February 27, 2025
    Inventors: Xin Jian CUI, Liu HAN
  • Patent number: 12224755
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: February 11, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Liu Han, Jing Ding, Qingchao Meng
  • Patent number: 12180834
    Abstract: A method for slope geological disaster treatment and mineral resource recovery includes the following steps: S1: dividing a mountain top into a plurality of treatment sections and treatment segments; S2, selecting an easy-to-slide area at the upper portion of a first treatment segment and blasting an easy-to-slide body to make the easy-to-slide body roll down to a bottom of the slope; S3, forming a regular initial slope bench; S4, mining coal at the coal seam in a grouped mining adit manner, and laying grouting pipelines in the primary mining adits; S5, forming closed mining adits; S6, excavating secondary mining adits at intervals of the primary mining adits in sequence; S7, continuing mining in an adjacent second treatment segment in the same manner; and S8, continuing mining the first treatment segment of the second treatment section in the same manner.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 31, 2024
    Assignee: CHINA UNIVERSITY OF MINING AND TECHNOLOGY
    Inventors: Shuzhao Chen, Liu Han, Cangyan Xiao, Meng Yang
  • Patent number: 12166487
    Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: December 10, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Tzu-Ying Lin, Liu Han, Jerry Chang Jui Kao, Qingchao Meng, Xiangdong Chen
  • Patent number: 11994027
    Abstract: The present invention discloses a dendritic reverse underground mining method for a thin coal seam at an end slope of a strip mine. The method includes the following steps: step S1: using a continuous coal mining machine to excavate a main adit toward a boundary of the strip mine along a seam floor; step S2: excavating secondary adits on two sides of the main adit obliquely in a forward direction of the main adit; step S3: transporting the excavated coal out of the main adit by the self-moving belt conveyors; step S4: after the excavating of a secondary adit of the secondary adits is ended, withdrawing the continuous coal mining machine and the self-moving belt conveyor from the secondary adit, and then excavating subsequent secondary adits of the secondary adits in a similar way; step S5: filling the secondary adits, and filling a goaf of the main adit.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 28, 2024
    Assignees: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, JIANGSU VOCATIONAL INSTITUTE OF ARCHITECTURAL TECHNOLOGY
    Inventors: Shuzhao Chen, Cangyan Xiao, Liu Han
  • Publication number: 20240097661
    Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
  • Publication number: 20240088128
    Abstract: A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Yang ZHOU, Liu HAN, Qingchao MENG, XinYong WANG, ZeJian CAI
  • Publication number: 20240048135
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 8, 2024
    Inventors: Huaixin XIAN, Liu HAN, Jing DING, Qingchao MENG
  • Patent number: 11876088
    Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: January 16, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED, TSMC CHINA COMPANY, LIMITED
    Inventors: Yang Zhou, Liu Han, Qingchao Meng, XinYong Wang, ZeJian Cai
  • Publication number: 20230402446
    Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
    Type: Application
    Filed: August 10, 2023
    Publication date: December 14, 2023
    Inventors: Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
  • Patent number: 11838026
    Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 5, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED
    Inventors: Huaixin Xian, Liu Han, Jing Ding, Qingchao Meng
  • Publication number: 20230342533
    Abstract: In some embodiments, a method of generating a cell in a layout diagram includes: selecting a cell from a library of standard cells, components of the cell defining an active circuit; identifying a dummy device within the cell that is disconnected from the active circuit within the cell; and connecting the dummy device to a target node of the active circuit.
    Type: Application
    Filed: May 12, 2022
    Publication date: October 26, 2023
    Inventors: Yiyun HUANG, Zhang-Ying YAN, Liu HAN, Qingchao MENG
  • Patent number: 11795643
    Abstract: The present invention discloses a method for constructing inner dump type strip mine pit bottom reservoirs section by section, specifically including the following steps: S1: processing end slopes: discarding clay at a lowest step of an inner waste dump of a strip mine; S2: discharging concrete to slope faces of lowest steps of the end slopes on two sides of a pit bottom; S3: sealing the bottom; S4: discarding gravel into a pit of the strip mine; S5: laying geotextile; S6: re-adopting clay on the lowest steps of the end slopes of the inner waste dump, so as to form a reservoir sealing isolation layer; S7: constructing a plurality of reservoirs step by step in an advancing direction of the strip mine; S8: storing water resources: completing installation of water storage wells; S9: completing installation of water fetching wells; S10: storing water resources.
    Type: Grant
    Filed: February 29, 2020
    Date of Patent: October 24, 2023
    Assignee: CHINA UNIVERSITY OF MINING AND TECHNOLOGY
    Inventors: Shuzhao Chen, Liu Han, Cangyan Xiao, Tao Shang
  • Patent number: 11673747
    Abstract: Provided herein is a method for constructing a pumping-injection well of a groundwater reservoir in a dump of an open-pit mine. The pumping-injection well includes a bottom pipe, intermediate pipes, and a top pipe in sequence from bottom to top connected from bottom to top. The method includes: arranging a rubble barrier around the pumping-injection well, and installing the bottom pipe of the pumping-injection well at a designed position of the pumping-injection well as a center of circle; continuing to install an intermediate pipe on the bottom pipe, and pile up a rubble pile; continuing to stack multiple intermediate pipes, and starting the construction of the groundwater reservoir; discarding discarded materials from the open-pit mine to form a dump; continuing to stack intermediate pipes to build an inverted trapezoidal surface sump around the pumping-injection well; and installing the top pipe and a well cover to form a complete pumping-injection well.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: June 13, 2023
    Assignees: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, CHN ENERGY Investment Group Co., LTD
    Inventors: Shuzhao Chen, Quansheng Li, Zhiguo Cao, Liu Han
  • Patent number: 11674393
    Abstract: A method for constructing a dam inside a dump of an inner-dump strip mine includes: taking an upper surface connection line of a primary water-resisting layer as upper filling reference datum boundary of an artificial water-resisting layer; arranging a dam foundation pit and a trapezoidal abutment on a midline of the dam foundation pit; building and reinforcing a step-shaped retaining dam core wall on the artificial water-resisting layer; laying a foundation impervious layer, waterproof geotextile, and an earth blanket on one side, close to the primary aquifer, of the retaining dam core wall; strengthening advance of a dumping working face on one side, away from the primary aquifer, of the retaining dam core wall, and dumping overburden of a strip mine to form a support; filling a space between the earth blanket and the primary aquifer to form a blocker; and proceeding with construction and forming a continuous retaining dam.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: June 13, 2023
    Assignees: China University of Mining and Technology, State Energy Investment Group Co. LTD, Jiangsu Vocational Institute of Architectural Technology
    Inventors: Shuzhao Chen, Quansheng Li, Liu Han, Cangyan Xiao
  • Publication number: 20230029848
    Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 2, 2023
    Inventors: Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
  • Publication number: 20230030467
    Abstract: A method for slope geological disaster treatment and mineral resource recovery includes the following steps: S1: dividing a mountain top into a plurality of treatment sections and treatment segments; S2, selecting an easy-to-slide area at the upper portion of a first treatment segment and blasting an easy-to-slide body to make the easy-to-slide body roll down to a bottom of the slope; S3, forming a regular initial slope bench; S4, mining coal at the coal seam in a grouped mining adit manner, and laying grouting pipelines in the primary mining adits; S5, forming closed mining adits; S6, excavating secondary mining adits at intervals of the primary mining adits in sequence; S7, continuing mining in an adjacent second treatment segment in the same manner; and S8, continuing mining the first treatment segment of the second treatment section in the same manner.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 2, 2023
    Applicant: CHINA UNIVERSITY OF MINING AND TECHNOLOGY
    Inventors: Shuzhao CHEN, Liu HAN, Cangyan XIAO, Meng YANG
  • Publication number: 20230030574
    Abstract: The disclosure discloses a method for constructing a pumping-injection well of a groundwater reservoir in a dump of an open-pit mine. The pumping-injection well includes a bottom pipe, intermediate pipes, and a top pipe in sequence from bottom to top connected from bottom to top. The method includes: arranging a rubble barrier around the pumping-injection well, and installing the bottom pipe of the pumping-injection well at a designed position of the pumping-injection well as a center of circle; continuing to install an intermediate pipe on the bottom pipe, and pile up a rubble pile; continuing to stack multiple intermediate pipes, and starting the construction of the groundwater reservoir; discarding discarded materials from the open-pit mine to form a dump; continuing to stack intermediate pipes to build an inverted trapezoidal surface sump around the pumping-injection well; and installing the top pipe and a well cover to form a complete pumping-injection well.
    Type: Application
    Filed: July 7, 2022
    Publication date: February 2, 2023
    Applicants: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, CHN ENERGY Investment Group Co.,LTD
    Inventors: Shuzhao CHEN, Quansheng LI, Zhiguo CAO, Liu HAN