Patents by Inventor Liu Hans
Liu Hans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097661Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
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Publication number: 20240088128Abstract: A method of manufacturing an IC structure includes configuring each of an n-well and a p-well in a first IC die to have a first portion extending in a first direction and second and third portions extending from the first portion in a second direction perpendicular to the first direction, and forming IC devices including a first pickup structure electrically connected to the n-well and a second pickup structure electrically connected to the p-well. Forming the IC devices includes forming a PMOS transistor in the second or third portion of the n-well and forming an NMOS transistor in the second or third portion of the p-well.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: Yang ZHOU, Liu HAN, Qingchao MENG, XinYong WANG, ZeJian CAI
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Publication number: 20240076354Abstract: The present invention features compositions and methods featuring ALT-803, a complex of an interleukin-15 (IL-15) superagonist mutant and a dimeric IL-15 receptor ?/Fc fusion protein useful for enhancing an immune response against a neoplasia (e.g., multiple myeloma, melanoma, lymphoma) or a viral infection (e.g., human immunodeficiency virus).Type: ApplicationFiled: October 31, 2023Publication date: March 7, 2024Inventors: Hing C. Wong, Peter Rhode, Bai Liu, Xiaoyun Zhu, Kai-Ping Han
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Publication number: 20240076444Abstract: The present invention relates to a polybutylene terephthalate composition, and an article derived from the polybutylene terephthalate composition comprising as component (A) polybutylene terephthalate (PBT) resin, as component (B) vinyl aromatic-based polymer comprising units which are derived from vinyl aromatic monomers, and as component (C) reinforcement agent.Type: ApplicationFiled: October 13, 2020Publication date: March 7, 2024Inventors: Chao Liu, Qiong Jie Han, Roland Helmut Kraemer, Zhen Ke Wei
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Publication number: 20240048135Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Inventors: Huaixin XIAN, Liu HAN, Jing DING, Qingchao MENG
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Patent number: 11876088Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.Type: GrantFiled: November 16, 2021Date of Patent: January 16, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED, TSMC CHINA COMPANY, LIMITEDInventors: Yang Zhou, Liu Han, Qingchao Meng, XinYong Wang, ZeJian Cai
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Publication number: 20230402446Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.Type: ApplicationFiled: August 10, 2023Publication date: December 14, 2023Inventors: Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
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Patent number: 11838026Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.Type: GrantFiled: June 29, 2021Date of Patent: December 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Huaixin Xian, Liu Han, Jing Ding, Qingchao Meng
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Publication number: 20230342533Abstract: In some embodiments, a method of generating a cell in a layout diagram includes: selecting a cell from a library of standard cells, components of the cell defining an active circuit; identifying a dummy device within the cell that is disconnected from the active circuit within the cell; and connecting the dummy device to a target node of the active circuit.Type: ApplicationFiled: May 12, 2022Publication date: October 26, 2023Inventors: Yiyun HUANG, Zhang-Ying YAN, Liu HAN, Qingchao MENG
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Patent number: 11795643Abstract: The present invention discloses a method for constructing inner dump type strip mine pit bottom reservoirs section by section, specifically including the following steps: S1: processing end slopes: discarding clay at a lowest step of an inner waste dump of a strip mine; S2: discharging concrete to slope faces of lowest steps of the end slopes on two sides of a pit bottom; S3: sealing the bottom; S4: discarding gravel into a pit of the strip mine; S5: laying geotextile; S6: re-adopting clay on the lowest steps of the end slopes of the inner waste dump, so as to form a reservoir sealing isolation layer; S7: constructing a plurality of reservoirs step by step in an advancing direction of the strip mine; S8: storing water resources: completing installation of water storage wells; S9: completing installation of water fetching wells; S10: storing water resources.Type: GrantFiled: February 29, 2020Date of Patent: October 24, 2023Assignee: CHINA UNIVERSITY OF MINING AND TECHNOLOGYInventors: Shuzhao Chen, Liu Han, Cangyan Xiao, Tao Shang
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Patent number: 11673747Abstract: Provided herein is a method for constructing a pumping-injection well of a groundwater reservoir in a dump of an open-pit mine. The pumping-injection well includes a bottom pipe, intermediate pipes, and a top pipe in sequence from bottom to top connected from bottom to top. The method includes: arranging a rubble barrier around the pumping-injection well, and installing the bottom pipe of the pumping-injection well at a designed position of the pumping-injection well as a center of circle; continuing to install an intermediate pipe on the bottom pipe, and pile up a rubble pile; continuing to stack multiple intermediate pipes, and starting the construction of the groundwater reservoir; discarding discarded materials from the open-pit mine to form a dump; continuing to stack intermediate pipes to build an inverted trapezoidal surface sump around the pumping-injection well; and installing the top pipe and a well cover to form a complete pumping-injection well.Type: GrantFiled: July 7, 2022Date of Patent: June 13, 2023Assignees: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, CHN ENERGY Investment Group Co., LTDInventors: Shuzhao Chen, Quansheng Li, Zhiguo Cao, Liu Han
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Patent number: 11674393Abstract: A method for constructing a dam inside a dump of an inner-dump strip mine includes: taking an upper surface connection line of a primary water-resisting layer as upper filling reference datum boundary of an artificial water-resisting layer; arranging a dam foundation pit and a trapezoidal abutment on a midline of the dam foundation pit; building and reinforcing a step-shaped retaining dam core wall on the artificial water-resisting layer; laying a foundation impervious layer, waterproof geotextile, and an earth blanket on one side, close to the primary aquifer, of the retaining dam core wall; strengthening advance of a dumping working face on one side, away from the primary aquifer, of the retaining dam core wall, and dumping overburden of a strip mine to form a support; filling a space between the earth blanket and the primary aquifer to form a blocker; and proceeding with construction and forming a continuous retaining dam.Type: GrantFiled: March 25, 2022Date of Patent: June 13, 2023Assignees: China University of Mining and Technology, State Energy Investment Group Co. LTD, Jiangsu Vocational Institute of Architectural TechnologyInventors: Shuzhao Chen, Quansheng Li, Liu Han, Cangyan Xiao
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Publication number: 20230030467Abstract: A method for slope geological disaster treatment and mineral resource recovery includes the following steps: S1: dividing a mountain top into a plurality of treatment sections and treatment segments; S2, selecting an easy-to-slide area at the upper portion of a first treatment segment and blasting an easy-to-slide body to make the easy-to-slide body roll down to a bottom of the slope; S3, forming a regular initial slope bench; S4, mining coal at the coal seam in a grouped mining adit manner, and laying grouting pipelines in the primary mining adits; S5, forming closed mining adits; S6, excavating secondary mining adits at intervals of the primary mining adits in sequence; S7, continuing mining in an adjacent second treatment segment in the same manner; and S8, continuing mining the first treatment segment of the second treatment section in the same manner.Type: ApplicationFiled: July 26, 2022Publication date: February 2, 2023Applicant: CHINA UNIVERSITY OF MINING AND TECHNOLOGYInventors: Shuzhao CHEN, Liu HAN, Cangyan XIAO, Meng YANG
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Publication number: 20230029848Abstract: A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.Type: ApplicationFiled: August 19, 2021Publication date: February 2, 2023Inventors: Liu HAN, Xin Yong WANG, Qingchao MENG, Huaixin XIAN, Jing DING
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Publication number: 20230030574Abstract: The disclosure discloses a method for constructing a pumping-injection well of a groundwater reservoir in a dump of an open-pit mine. The pumping-injection well includes a bottom pipe, intermediate pipes, and a top pipe in sequence from bottom to top connected from bottom to top. The method includes: arranging a rubble barrier around the pumping-injection well, and installing the bottom pipe of the pumping-injection well at a designed position of the pumping-injection well as a center of circle; continuing to install an intermediate pipe on the bottom pipe, and pile up a rubble pile; continuing to stack multiple intermediate pipes, and starting the construction of the groundwater reservoir; discarding discarded materials from the open-pit mine to form a dump; continuing to stack intermediate pipes to build an inverted trapezoidal surface sump around the pumping-injection well; and installing the top pipe and a well cover to form a complete pumping-injection well.Type: ApplicationFiled: July 7, 2022Publication date: February 2, 2023Applicants: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, CHN ENERGY Investment Group Co.,LTDInventors: Shuzhao CHEN, Quansheng LI, Zhiguo CAO, Liu HAN
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Publication number: 20220405456Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.Type: ApplicationFiled: June 29, 2021Publication date: December 22, 2022Inventors: Huaixin XIAN, Liu HAN, Jing DING, Qingchao MENG
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Publication number: 20220399326Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.Type: ApplicationFiled: November 16, 2021Publication date: December 15, 2022Inventors: Yang ZHOU, Liu HAN, Qingchao MENG, XinYong WANG, ZeJian CAI
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Publication number: 20220333486Abstract: A method for constructing a dam inside a dump of an inner-dump strip mine includes: taking an upper surface connection line of a primary water-resisting layer as upper filling reference datum boundary of an artificial water-resisting layer; arranging a dam foundation pit and a trapezoidal abutment on a midline of the dam foundation pit; building and reinforcing a step-shaped retaining dam core wall on the artificial water-resisting layer; laying a foundation impervious layer, waterproof geotextile, and an earth blanket on one side, close to the primary aquifer, of the retaining dam core wall; strengthening advance of a dumping working face on one side, away from the primary aquifer, of the retaining dam core wall, and dumping overburden of a strip mine to form a support; filling a space between the earth blanket and the primary aquifer to form a blocker; and proceeding with construction and forming a continuous retaining dam.Type: ApplicationFiled: March 25, 2022Publication date: October 20, 2022Applicants: China University of Mining and Technology, State Energy Investment Group Co. LTD, Jiangsu Vocational Institute of Architectural TechnologyInventors: Shuzhao CHEN, Quansheng LI, Liu HAN, Cangyan XIAO
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Patent number: 11456292Abstract: A semiconductor device includes a substrate, a first gate structure, a second gate structure, a third gate structure, and a first source/drain region. The first, second, and third gate structures are above the substrate and arranged in a first direction. The first, second, and third gate structures extend in a second direction different from the first direction, and the second gate structure is between the first and third gate structures. The first source/drain region is between the first and third gate structures, and the first source/drain region is at one end of the second gate structure.Type: GrantFiled: May 11, 2020Date of Patent: September 27, 2022Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITEDInventors: Xin-Yong Wang, Yang Zhou, Liu Han
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Publication number: 20220267974Abstract: The present invention discloses a method for constructing inner dump type strip mine pit bottom reservoirs section by section, specifically including the following steps: S1: processing end slopes: discarding clay at a lowest step of an inner waste dump of a strip mine; S2: discharging concrete to slope faces of lowest steps of the end slopes on two sides of a pit bottom; S3: sealing the bottom; S4: discarding gravel into a pit of the strip mine; S5: laying geotextile; S6: re-adopting clay on the lowest steps of the end slopes of the inner waste dump, so as to form a reservoir sealing isolation layer; S7: constructing a plurality of reservoirs step by step in an advancing direction of the strip mine; S8: storing water resources: completing installation of water storage wells; S9: completing installation of water fetching wells; S10: storing water resources.Type: ApplicationFiled: February 29, 2020Publication date: August 25, 2022Inventors: Shuzhao CHEN, Liu HAN, Cangyan XIAO, Tao SHANG